Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . This Office Action responds to the Application filed on 9/29/2023 and IDS filed on 2/21/2025 and 3/10.2025. Claims 1-20 are pending.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1,8,15 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Duenas et al. (US Patent Application No. 2023/0205658 A1).
As per claims 1,8,15, Fig. 4 illustrate the elements of the claims comprising the circuitry/power manager circuit (controller 410), to update the operating parameters of a plurality of functional blocks (i.e., 404 which represents a plurality of functional blocks—see paragraphs [0052]. [0054]), including a given power supply voltage and frequencies assigned to various functional blocks—see paragraph [0053]-[0054], wherein operating parameters include setting (some or all of the functional blocks) to operate at lower clock frequencies (which corresponds to the target frequency) and other functional blocks to the normal or given frequency, which is higher than the target frequency; and execute, by the plurality of functional blocks, a workload using the operating parameters (see paragraph [0054], which is executed or caused to be implemented the workload by the platform management driver (418); wherein the first processor and second processor could the “CPU or GPU” which comprises the functional block 404 (see paragraph [0052]).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2-4,9-11,16-19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Duenas et al. (US Patent Application No. 2023/0205658 A1) in view of Hanson et al. (US Patent Application Publication No. 20240072806 A1).
As per claims 2,9,16, Duenas et al. teach all of the elements of claims 1, 8, and 15, from which the respective claims depend, as discussed in the rejections of claims 1, 8, 15 above, including assigning certain functional blocks to higher performance, which could be set at the time of manufacture (see paragraphs [0019], [0021], [0060]) but failed to teach that this assignment is based on manufacturing variations. Hanson et al. teach that “a voltage is set to a higher value at “slow” process corners and a lower value at “fast” process corners to compensate for manufacturing variations, ensuring that logic gate delay remains approximately constant across all manufacturing conditions” (see paragraph [0039]). It would have been obvious to one of ordinary skilled in the art at the time of the effective filing date of the invention further incorporate the teachings of Hanson et al. into the method/system of Duenas et al. because incorporation would further allow the different functional logic blocks to function properly to account to manufacturing variations as taught by Hanson et al. and intended by Duenas et al..
As per claims 3, 10, 17¸ Duenas et al. also teach determining a plurality of power supply voltages, each being a power supply voltage supported by a separate one of the plurality of functional blocks when using the target clock frequency (see paragraphs [0017], [0053], i.e., dynamic setting of voltages for various functional blocks are dynamically determined and configured).
As per claims 4, 11, 18-19, Duenas et at. also teach that the given power supply voltage is a maximum power supply voltage of the plurality of power supply voltages since the voltages are reduced from this maximum supply voltage to adjust the system performance for maximizing performance, including determining operating clock frequency to use, given the particular power supply voltage (see paragraphs [0001], [0053]).
Claim(s) 5,12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Duenas et al. (US Patent Application No. 2023/0205658 A1) in view of Luan et al. (US Patent Application Publication No. 20220318470 A1).
As per claims 5, 12, Duenas et al. teach all of the elements of claims 1, 8, from which the respective claims depend as discussed in the rejections of claims 1 and 8 above, including assigning certain functional blocks to higher frequencies than other functional blocks (see paragraphs [0053], [0054], [0060]) but failed to teach that this assignment to higher clock frequencies is based on at least in part on the physical position of a particular functional block (i.e., second functional block) relative to the other functional blocks (i.e., first and third functional blocks). Such use of higher frequencies to reduce the delay due to longer distances (i.e., physical position of a certain logic block relative to another functional block) is known in the art and is further taught by Luan et al. (see paragraphs [[0031]. [0163], [0169]). It would have been obvious to one of ordinary skilled in the art at the time of the effective filing date of the invention to further incorporate the teachings of Luan et al. into the method/system of Duenas et al. because such incorporation would further allow the difference functional blocks to operate properly at the higher frequencies than other functional blocks, accounting delays due to longer distances among the functional blocks as further taught by Luan et al..
Claim(s) 6-7,13-14,20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Duenas et al. (US Patent Application No. 2023/0205658 A1) in view of Hanson et al. (US Patent Application Publication No. 20240072806 A1) and Davis et al. (US Patent Application Publication No US 20230305993 A1 ).
A1 As per claims 6-7,13-14,20, Duenas et al. in view of Hanson et al. teach all of the elements of claims 2, 9, and 16, from which the respective claims depend, as discussed in the rejections of claims 2, 9 and 16 above, including the functional blocks could be chips, (see Duenas et al., paragraph [0015], [0027], [0036]), but failed to teach that each of the plurality of functional blocks is an active interposer die comprising a communication fabric, wherein the second functional block routes packets between sources and destinations that include at least the first functional block and the third functional block. Such use of interposer and data packets to communicate among the functional blocks (i.e., chips, or chiplets or die) are further taught by Davis et al. (see paragraphs [0106], [0138[], [0184]). It would have been obvious to one of ordinary skilled in the art at the time of the effective filing date of the invention to further incorporate the teachings of Davis et al into the method/system of Duenas et al. in view of Hanson et al. because such incorporation would further allow for communication among functional blocks are fabricated as separate chips or chiplets, interconnect by an interposer as further taught by Davis et al..
Conclusion
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/PHALLAKA KIK/Primary Examiner, Art Unit 2851 July 2, 2026
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