DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 2, 6, 11, 12, 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Brennan US 2022/0318944 in view of Clark US 2021/0407171.
Regarding claims 1, 11: Brennan teaches a processing unit (fig. 1) comprising:
a parameter cache (L2 cache, paragraph 0009); and scheduling circuitry (management circuitry, paragraph 10 with SPI of paragraph 9) configured to: read one or more attributes (fetches the attributes from the L2 cache, paragraph 0009) of a first primitive (primitives, paragraph 0009 note the pixel waves are generated from primitives) from the parameter cache to initialize a first pixel wave using the one or more attributes (perform pixel processing on the pixel wave using attributes retrieved from the L2 cache, paragraph 0009 note: the step of fetching attributes ready for processing the pixel waves is interpretated as initialized the pixel waves); and reading the one or more attributes from the parameter cache to initialize a second pixel wave (a wave group which includes one or more waves, paragraph 0009 implies that there are more than one pixel wave to be launched and processed).
Brennan does not teach: omit reading the one or more attributes from the parameter cache to initialize a second pixel wave in response to a determination that the second pixel wave is associated with the first primitive.
Clark, in the same area of data processing, teaches to store data used in processing in local memory 318 which temporary stores data for tor the nodes when data has been fetched from memory 304 so this data can be reused e.g., for performing intersection tests for rays with the nodes define by the node data (paragraph 0145) Clark also teaches to omit reading one or more node data (paragraph 0142, data defining the region represented by an implicitly represented node is not explicitly included as part of the stored data, note: not part of the stored data implies that the data is not read from memory 304 into local memory 318) in response to a determining that the implicit node (DE) is associated with explicit node (HIJK) (see paragraph 0146, in step S606 the node processing logic 320, infers, from the received data, data defining the region(s) represented by the implicitly represented nodes. For example, the node processing logic 320 can infer the data defining the region represented by the implicitly represented node D using data defining the regions represented by the nodes H and I. In other words, the system inherently/obviously, needs to determined that node D is associated with the data representing nodes H and I so that the system can reused the fetched data representing node H and I to be used for node D without reading node data belongs to D from memory 304 into local memory 318)(also see paragraph 0138).
Therefore, it would have been obvious to a person with ordinary skill in the art to have modified Brennan to provide local memory unit to store attribute read from the parameter cache for each compute units of Brennan such that the system can omit reading the one or more attributes of the primitive of the second pixel wave from the parameter cache to initialize a second pixel wave in response to a determination that the second pixel wave is associated with the first primitive.
The reason of doing so would have allowed the system to reduce the amount of data to be read and hence increase processing efficiency.
Regarding claims 2, 12: Brennan in view of Clark teaches the processing unit of claim 11, further comprising a plurality of compute units (compute units paragraph 0012, Brennan) that are each associated with a local data store (LDS) (see rejection of claim 11 that each of the CU is modified to have a local memory to store attribute data read from parameter cache), and wherein to initialize the first pixel wave comprises to store the one or more attributes read from the parameter cache in one or more blocks of an LDS that is associated with one compute unit of the plurality of compute units, the one compute unit being one of one or more compute units assigned to render the first pixel wave (the compute units in the shader hub then perform pixel processing on the pixel waves, paragraph 0009, Brennan).
Regarding claims 6, 16: Brennan teaches the processing unit of claim 12, further comprising rendering the first and second pixel waves by the one or more assigned compute units using the one or more attributes stored in the one or more LDS blocks. (see rejection of claim 11, also see paragraph 0009, the compute units in the shader hub then perform pixel processing on the pixel waves using the attributes retrieved from L2 cache).
Claim(s) 3, 5, 13, 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Brennan US 2022/0318944 in view of Clark US 2021/0407171 and Gooding US 2016/0019154.
Regarding claims 3, 13: Brennan does not teach: the processing unit of claim 12, further comprising a tracking array to store one or more indications of the one or more LDS blocks in which the one or more attributes are stored.
Gooding teaches a tracking array (tracking array paragraph 45) to store one or more indications (memory address 372 paragraph 45) of the one or more memory in which the one or more data (prefetch list, paragraph 45) are stored.
Since the LDS block is a type of memory and the attribute data stored in the LDS block of Brennan as modified, it would have been obvious to a person with ordinary skill in the art to have modified Brennan to include: a tracking array to store one or more indications of the one or more LDS blocks in which the one or more attributes are stored.
The reason of doing so would have improved the efficiency of memory accesses, paragraph 0003).
Regarding claims 5, 15: Gooding teaches The processing unit of claim 13, wherein to maintain the tracking array includes to set a bit value at a location in the tracking array (see 380 of fig. 3B, note: inherently, all computers storing data in memory in the unit of bits) that corresponds to an LDS block in which at least one attribute of the one or more attributes of the first primitive is stored (see rejection of claim 13).
Claim(s) 4, 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Brennan US 2022/0318944 in view of Clark US 2021/0407171, Gooding US 2016/0019154 and Ash US 2006/0227702.
Regarding claims 4, 14: Brennan does not teach the processing unit of claim 13, wherein the scheduling circuitry is further configured to maintain the tracking array, and wherein to maintain the tracking array includes to store the tracking array in the parameter cache.
Ash teaches to store a tracking array in a cache (paragraph 0053).
Since the management system of Brennan is used to reserve requested space in L2 cache and for storing primitives (note the attributes of primitives can be viewed as parameter), it would have been obvious to a person with ordinary skill in the art to have modified Brennan to include: wherein the scheduling circuitry (management circuitry) is further configured to maintain the tracking array, and wherein to maintain the tracking array includes to store the tracking array in the parameter cache.
The reason of doing so would have allowed data in tracking array to be quickly accessed to improve the overall performance of the system of Brennan.
Claim(s) 7, 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Brennan US 2022/0318944 in view of Clark US 2021/0407171 and Johnson US 2001/0008009.
Regarding claims 7, 17: Brennan does not teach the processing unit of claim 11, wherein the scheduling circuitry is further configured to compare parameter cache addresses of vertices associated with the second pixel wave to parameter cache addresses of vertices associated with the first primitive in order to determine that the second pixel wave is associated with the first primitive.
Brennan teaches to store attributes into parameter cache (attributes from the shader output are stored in the reserved space in the L2 cache, paragraph 0009) generated from vertices (fig. 2, vertex shader paragraph 0019) associated with pixel wave (pixel wave, paragraph 0009) to be fetched out from the L2 cache into the compute unit for processing (paragraph 0009).
In rejection of claims 1, 11, the attributes fetch out from L2 cache is to be stored in a local memory before being fetched into the compute unit for processing.
Johnson teaches to fetch data from main memory (paragraph 0006) into another memory (cache, paragraph 0006) including main memory location of the data request by a processor to be processed. The data is associated with the main memory address and stored in the another memory (fully associated cache stores not only the data in the line, but also stores the line address of the address as a tag in association with the line of data, paragraph 0008). Johnson paragraph 0008 further teaches the next time the processor asserts a main memory address, the cache compares that address with the tag stored in the cache. If a match is found, the request data is provided to the processor from the cache.
Therefore, it would have been obvious to a person with ordinary skill in the art to have modified Brennan to include: wherein the scheduling circuitry is further configured to compare parameter cache addresses (analogy to the main memory address of the data being currently requested) of vertices associated with the second pixel wave (analogy to the data being currently requested to be processed) to parameter cache addresses (analogy to the main memory address of the data have been processed and stored in the cache) of vertices associated with the first primitive (analogy to the data that has been processed and stored in the cache) in order to determine that the second pixel wave is associated with the first primitive (note: if there is a match, implies the second wave is associated with the first primitive by having the same attributes).
The reason of doing so would have allowed data stored in the local memory to be reused without having to re-fetch from the cache to speed up processing time and improving processing efficiency.
Claim(s) 8, 9, 18, 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Brennan US 2022/0318944 in view of Clark US 2021/0407171 and Nordlund US 2013/0021358.
Regarding claims 8, 18: Brennan does not teach: the processing unit of claim 11, wherein the scheduling circuitry is further configured to identify the first primitive as a large primitive based on a quantity of pixels associated with the first primitive.
Norlund teaches to identify a primitive as a large primitive based on a quality of pixels associated with the primitive (paragraph 0028, classify the primitive as either large primitive or small primitives based on a metric indicative of the area of the primitive to be rasterized, paragraph 0014, metric indicative of the area of the primitive to be rendered, e.g. the number of screen pixels covered by a graphic primitive).
Therefore, it would have been obvious to a person with ordinary skill in the art to have modified Brennan to include: wherein the scheduling circuitry is further configured to identify the first primitive as a large primitive based on a quantity of pixels associated with the first primitive.
The reason of doing so would have optimized the processing of primitives (see paragraph 0002, Norlund.
Regarding claims 9, 19: Brennan as modified teaches the processing unit of claim 11, wherein the scheduling circuitry is further configured to identify the first primitive as a large primitive based on a quantity of shader operations required to render the first primitive. (see rejection of claim 18).
In rejection of claim 18, it was shown that Brennan as modified teach wherein the scheduling circuitry is further configured to identify the first primitive as a large primitive based on a quantity of pixels associated with the first primitive.
Brennan, paragraph 0009, further teaches the compute units in the shader hub then perform pixel processing on the pixel waves using attributes retrieved from the L2 Cache. Obviously, the more pixels there are in the pixel waves of a primitive, the more shader operations required to render the primitive in the pixel waves and vice versa. Therefore, it would have been obvious to a person with ordinary skill in the art to use the quantity of shader operation to determine whether the primitive is large for the reason of optimizing the processing of primitives.
Claim(s) 10, 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Brennan US 2022/0318944 in view of Clark US 2021/0407171 and further in view of Uhrenholt US 2022/0319111 and Hao US 20240233263.
Regarding claims 10, 20: Brennan does not teach the processing unit of claim 11, wherein the scheduling circuitry is further configured to identify the first primitive as a large primitive based on a quantity of memory required to store attributes associated with the first primitive.
Uhrenholt paragraph 0216 teaches the measure of the size of the primitive ….can be set as desired, e.g. to balance memory bandwidth… the threshold is in an embodiment set according to a cost calculation which accounts for the memory bandwidth and arithmetic processing cost associated with performing processing of one or more non-position attributes…
Hao, paragraph 0088 teaches the more the number of attributes of the primitive, the less the number of primitives that can be stored. This implies attributes in a primitive are using up storage.
In Brennan, the processing of attributes/primitive requires memory (paragraph 0009, output are stored in the reserved space in the L2 cache….the compute units in the shader hub then perform pixel processing on the pixel waves using the attributes retrieved from the L2 cache).
Therefore, it would have been obvious to a person with ordinary skill in the art to have modified Brennan to include: wherein the scheduling circuitry is further configured to identify the first primitive measured as a large primitive based on a quantity of memory required to store attributes associated with the first primitive.
The reason of doing so would have allowed the system to balance memory bandwidth such that the whole processing system can be functioned properly and efficiently.
Response to Arguments
Applicant's arguments filed 1/12/2026 have been fully considered but they are not persuasive.
Applicant, page 12 argues the office does not appear to provide how the system might work after the combination has been considered.
In reply: Brennan, paragraph 9 teaches the compute units in the shader hub then perform pixel processing on the pixel waves using the attributes retrieved from the L2 cache. This L2 cache is equivalent to the parameter cache in the claim. The “perform pixel processing on the pixel waves” inherently requires the attributes/parameters to be ready to get into the compute units to process the pixel waves. This step is equivalent to “initialized a pixel waves” in the claim.
Clark, paragraph 0145, teaches “the receiving logic 316 passes the node data…that it has received from the memory 304 in the local memory 318 for storage. The local memory 318 temporarily stores data for the node when that data has been fetched from the memory 304 so this data can be reused, e.g., for performing intersection tests for the rays with the nodes defined by the node data, without re-fetching the node data from the memory 304. The node data is provided from the local memory 318 to the node processing logic 320.
The memory 304 is analogy to L2 cache L2 of Brennen, the node processing logic 320 is analogy to the compute unit of Brennan. This teaching by Clark learned by a person with ordinary skill in the art is to store the data that is used for processing for a processing unit in a local memory of the processing unit after it is fetched from another memory so that the data can be reused without re-fetching the data from the another memory. Such design of Clark can clearly reduce the processing time as it takes time to fetch data each time the data is used again.
The compute units of Brennan are used to process pixel waves using attributes and parameter. The attributes and parameter used to process each pixel wave (the first pixel wave and the second pixel wave) may be the same or may not be the same. If the attributes used to process the first pixel wave and the second pixel wave are the same, it would have been obvious to a person with ordinary skill in the art, after reading Clark’s teaching to have provided a local memory to store the attributes used to process the first pixel wave and to reuse the attribute for the pixel wave to process the second pixel wave without re-fetching the attributes from L2 cache. Therefore, the combination of Brennan and Clark teaches omit reading the one or more attributes from the parameter cache to initialize a second pixel wave in response to a determination that the second pixel wave is associated with the first primitive (in the situation that the attributes used to process the first pixel wave can also be re-used to process the second pixel wave).
Applicant’s argument that one cannot apply Clark’s logic -calculating a parent node spatial bounds from its children -to a rasterized attribute fetch has been considered.
In response to applicant's argument that Brennan and Clark is nonanalogous art, it has been held that a prior art reference must either be in the field of the inventor’s endeavor or, if not, then be reasonably pertinent to the particular problem with which the inventor was concerned, in order to be relied upon as a basis for rejection of the claimed invention. See In re Oetiker, 977 F.2d 1443, 24 USPQ2d 1443 (Fed. Cir. 1992). In this case, as previous explanation, examiner is not applying Clark’s logic -calculating a parent node spatial bounds from its children -to a rasterized attribute.
Examiner is using Clark’s logic of using a local memory to stored and reused data for another processing (see explanation above) to apply to Brennan to store and reuse the attribute data for processing subsequent pixel wave without re-fetching the attribute from L2 Cache of Brennan.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KING Y POON whose telephone number is (571)270-0728. The examiner can normally be reached Monday-Friday.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Alexander Beck can be reached at 571-272-3750. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/KING Y POON/ Supervisory Patent Examiner, Art Unit 2617
Prosecution Insights