DETAILED ACTION
General Remarks
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
When responding to this office action, applicants are advised to provide the examiner with line numbers and page numbers in the application and/or references cited to assist the examiner in locating appropriate paragraphs.
Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
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Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-20 are rejected under 35 U.S.C. 103 as being unpatentable over Scanlan et al. (US 20130280826 A1), hereinafter “Scanlan,” in view of Kinsman et al. (US 20020027257 A1), hereinafter “Kinsman.”
Re: Independent Claim 1, Scanlan discloses an assembly (Fig. 1A shows a panel (102) including a plurality of device units (104); See Fig. 2B) comprises:
an integrated circuit (IC) chip having wire bond pads (Fig. 2B: IC chip/semiconductor die unit 152 with bond pad 105; Fig. 13H: IC chip (334) with wire bond pads (342));
… bumps coupled to the wire bond pads of th e IC chip (Fig. 12B shows an embodiment with bumps (348) coupled to wire bond pads (342) of IC chip (334); Also see Fig. 13H);
an overmold that encapsulates the IC chip (See Fig. 13B: encapsulant (366); Fig. 13H: IC chip (334) and overmold/encapsulant (366));
ball contact pads coupled to the overmold (Fig. 13H: ball contact pads/under bump metallurgy (UBM) (394) which are coupled to the overmold (366)), wherein the ball contact pads are electrically coupled to the wire bond pads by way of the ball bumps (Fig. 13H: ball contact pads/UBM (394) are electrically coupled to wire bond pads (342) via ball bumps (356)); and
solder balls coupled to the ball contact pads (Fig. 13H: solder balls (396) are coupled to ball contact pads/UBM (394); ¶ [0152]: bump material can be solder).
However, Scanlan does not specifically disclose ball bumps.
In a similar field of endeavor, Kinsman discloses ball bumps (Fig. 1A shows ball bumps (20) deposited on bond pads (12) which are connected to IC chip (14)).
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the manufacturing process disclosed by Scanlan to include features disclosed by Kinsman to use ball bumping using conventional wire bonding tools to reduce costs (Kinsman, ¶ [0005]) in order to create an improved method for forming a chip scale package that does not significantly complicate the manufacturing or handling of the integrated circuitry and that is repeatable and reliable when using conventional mass production manufacturing techniques (See Kinsman, ¶ [0011]).
Re: claim 2, the combination of Scanlan in view of Kinsman discloses all the limitations of claim 1 on which this claim depends.
Scanlan also discloses further comprising vias in the overmold that couple to the ball bumps on the IC chip (See Figs. 13E-13G; ¶ [0150] FIG. 13G, continuing from FIG. 13F, shows a second portion 390b of conductive layer 390 disposed over semiconductor die 334, interconnect 356 (i.e., ball bumps), encapsulant 366 (i.e., overmold), and insulating layer 388. Second portion 390b (i.e., vias) of conductive layer 390 is formed according to actual positions of semiconductor die 334 and interconnects 356).
Re: claim 3, the combination of Scanlan in view of Kinsman discloses all the limitations of claim 1 on which this claim depends.
Scanlan also discloses, further comprising:
vias in the overmold that couple to the ball bumps on the IC chip (See Figs. 13E-13G; ¶ [0150]); and
trace lines (Figs. 13E and 13G: trace lines 390b) between ball contact pads (Fig. 13H: 394) to the vias of the IC chip (Figs. 13E and 13G: 390b).
Re: claim 4, the combination of Scanlan in view of Kinsman discloses all the limitations of claim 1 on which this claim depends.
Scanlan also discloses further comprising vias in the overmold that couple to the ball bumps on the IC chip (See Figs. 13E-13G; ¶ [0150]); and
conductive material that fills the vias (Fig. 13E: 390a and 390b; ¶ [0143]: Conductive layer 390 can be one or more layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable electrically conductive material.).
Re: claim 5, the combination of Scanlan in view of Kinsman discloses all the limitations of claim 1 on which this claim depends.
Kinsman further discloses wherein the overmold has a sufficiently thin dimension so as to expose at least a portion of the ball bumps on the IC chip (¶ [0033]: “FIG. 2 depicts how encapsulant material 30 may be applied to both the active surface 14… but not to overfill same to the point of being level with the top surfaces of intermediate conductive elements 20... If completely covered, the upper ends of intermediate conductive elements 20 may be exposed by abrasive planarization, or the encapsulant material 30 selectively etched to expose the upper ends.” In other words, the overmold/encapsulant (30) is filled to a height where a portion of the ball bumps/conductive elements (20) on the IC remain exposed.).
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the manufacturing process disclosed by Scanlan to create an improved method for forming a chip scale package that does not significantly complicate the manufacturing or handling of the integrated circuitry and that is repeatable and reliable when using conventional mass production manufacturing techniques. (See Kinsman, ¶ [0011]).
Re: claim 6, the combination of Scanlan in view of Kinsman discloses all the limitations of claim 1 on which this claim depends.
Scanlan also discloses further comprising trace lines (Figs. 13E and 13G: trace lines (390b)) that couple the ball contact pads (Fig. 13H: ball contact pads (394)) to the ball bumps on the IC chip (Figs. 13E and 13G: trace lines (390b) couple to ball bumps (356) on IC chip (334)).
Re: claim 7, the combination of Scanlan in view of Kinsman discloses all the limitations of claim 1 on which this claim depends.
Scanlan further discloses wherein the assembly is built into an array of assemblies (Fig. 1A shows a panel (102) including a plurality of device units (104), i.e., array of assemblies; Fig. 13H: assemblies post singulation).
Re: Independent claim 8, Scanlan discloses a system comprising (Abstract: An adaptive patterning method and system for fabricating panel based package structures):
one or more processors (¶ [0078]: processor); and
logic encoded in one or more non-transitory computer-readable storage media for execution by the one or more processors and when executed operable to cause the one or more processors to perform operations comprising (¶ [0078]: Certain embodiments may be implemented as a computer program product that may include instructions stored on a non-transitory machine-readable medium. These instructions may be used to program a general-purpose or special-purpose processor to perform the described operations):
applying … bumps to wire bond pads of an integrated circuit (IC) chip [Fig. 12B: ball bumps (348); ¶ [0124]: Electrical interconnects or copper posts, pillars, or columns 348 are formed over, and connected to, conductive layer 342. Interconnects 348 can be formed directly on conductive layer 342 using patterning and metal deposition processes such as printing, PVD, CVD, sputtering, electrolytic plating, electroless plating, metal evaporation, metal sputtering, or other suitable metal deposition process.];
encapsulating the IC chip with an overmold (Fig. 13B shows encapsulant (366) being deposited over IC chip (334));
building ball contact pads on the overmold (Fig. 13H shows ball contact pads (394)), wherein the ball contact pads are electrically coupled to the wire bond pads by way of the ball bumps (Fig. 13H: ball contact pads/UBM (394) are electrically coupled to wire bond pads (342) via ball bumps (356)); and
applying solder balls to the ball contact pads (Fig. 13H: solder balls (396) are coupled to ball contact pads/UBM (394); ¶ [0152]: An electrically conductive bump material is deposited over UBMs 394 and conductive layer 390 using an evaporation, electrolytic plating, electroless plating, ball drop, or screen printing process… bump material can be solder).
However, Scanlan does not specifically disclose ball bumps.
In a similar field of endeavor, Kinsman discloses ball bumps (Fig. 1A shows ball bumps (20) deposited on bond pads (12) which are connected to IC chip (14)).
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the manufacturing process disclosed by Scanlan to include features disclosed by Kinsman to use ball bumping using conventional wire bonding tools to reduce costs (Kinsman, ¶ [0005]) in order to create an improved method for forming a chip scale package that does not significantly complicate the manufacturing or handling of the integrated circuitry and that is repeatable and reliable when using conventional mass production manufacturing techniques (See Kinsman, ¶ [0011]).
Re: claim 9, the combination of Scanlan in view of Kinsman discloses all the limitations of claim 8 on which this claim depends.
Scanlan further discloses wherein the logic when executed is further operable to cause the one or more processors to perform operations (¶ [0078]: computer program product that may include instructions… These instructions may be used to program a general-purpose or special-purpose processor to perform the described operations) comprising drilling vias in the overmold to the ball bumps on the IC chip (¶ [0141] In FIG. 13E, a portion of insulating layer 388 is removed by etching, laser drilling, mechanical drilling, or other suitable process to form openings completely through insulating layer 388 to expose interconnects 356.).
Re: claim 10, the combination of Scanlan in view of Kinsman discloses all the limitations of claim 8 on which this claim depends.
Scanlan further discloses wherein the logic when executed is further operable to cause the one or more processors to perform operations (¶ [0078]: computer program product with instructions may be used to program a general-purpose or special-purpose processor to perform the described operations) comprising:
drilling vias in the overmold to the ball bumps on the IC chip (See (¶ [0141); and
drawing trace lines from the ball contact pads to the vias of the IC chip (Figs. 13E and 13G: trace lines (390b); Fig. 13H: ball contact pads (394); ¶ [0150] FIG. 13G, continuing from FIG. 13F, shows a second portion 390b of conductive layer 390 disposed over semiconductor die 334, interconnect 356 (i.e., ball bumps), encapsulant 366 (i.e., overmold), and insulating layer 388. Second portion 390b (i.e., vias) of conductive layer 390 is formed according to actual positions of semiconductor die 334 and interconnects 356).
Re: claim 11, the combination of Scanlan in view of Kinsman discloses all the limitations of claim 8 on which this claim depends.
Scanlan further discloses wherein the logic when executed is further operable to cause the one or more processors to perform operations (¶ [0078]: computer program product that may include instructions… These instructions may be used to program a general-purpose or special-purpose processor to perform the described operations) comprising:
drilling vias in the overmold to the ball bumps on the IC chip (See Figs. 13E-13G; ¶ [0150]); and
filling the vias with a conductive material (Fig. 13E: 390a and 390b; ¶ [0143]: Conductive layer 390 can be one or more layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable electrically conductive material).
Re: claim 12, the combination of Scanlan in view of Kinsman discloses all the limitations of claim 8 on which this claim depends.
Kinsman further discloses wherein the overmold has a sufficiently thin dimension so as to expose at least a portion of the ball bumps on the IC chip (¶ [0033]: “FIG. 2 depicts how encapsulant material 30 may be applied to both the active surface 14… but not to overfill same to the point of being level with the top surfaces of intermediate conductive elements 20... If completely covered, the upper ends of intermediate conductive elements 20 may be exposed by abrasive planarization, or the encapsulant material 30 selectively etched to expose the upper ends.” In other words, the overmold/encapsulant (30) is filled to a height where a portion of the ball bumps/conductive elements (20) on the IC remain exposed.).
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the manufacturing process disclosed by Scanlan to create an improved method for forming a chip scale package that does not significantly complicate the manufacturing or handling of the integrated circuitry and that is repeatable and reliable when using conventional mass production manufacturing techniques. (See Kinsman, ¶ [0011]).
Re: claim 13, the combination of Scanlan in view of Kinsman discloses all the limitations of claim 8 on which this claim depends.
Scanlan further discloses wherein the logic when executed is further operable to cause the one or more processors to perform operations (¶ [0078]: computer program product with instructions may be used to program a general-purpose or special-purpose processor to perform the described operations) comprising drawing trace lines from the ball contact pads to the ball bumps on the IC chip (Figs. 13E and 13G: trace lines (390b); Fig. 13H: ball contact pads (394); Figs. 13E and 13G: trace lines (390b) couple to ball bumps (356) on IC chip (334); ¶ [0053]: multiple dielectric layers and device interconnect traces, which may or may not be associated with the RDL, are formed in accordance with the principles described herein).
Re: claim 14, the combination of Scanlan in view of Kinsman discloses all the limitations of claim 8 on which this claim depends.
Scanlan further discloses wherein the logic when executed is further operable to cause the one or more processors to perform operations (¶ [0078]: computer program product with instructions may be used to program a general-purpose or special-purpose processor to perform the described operations) comprising performing a singulation process on an assembly containing the IC chip (¶ [0076]: a lot of die packages may be singulated from a panel or reticulated wafer.), wherein the assembly is built into an array of assemblies (See Fig. 1A).
Re: Independent claim 15, Scanlan discloses a computer-implemented method (¶ [0078]: computer program product with instructions may be used to program a general-purpose or special-purpose processor to perform the described operations) comprising:
applying … bumps to wire bond pads of an integrated circuit (IC) chip (Fig. 12B: ball bumps (348); See ¶ [0124]);
encapsulating the IC chip with an overmold (Fig. 13B shows encapsulant (366) being deposited over IC chip (334));
building ball contact pads on the overmold (Fig. 13H shows ball contact pads (394)), wherein the ball contact pads are electrically coupled to the wire bond pads by way of the ball bumps (Fig. 13H: ball contact pads/UBM (394) are electrically coupled to wire bond pads (342) via ball bumps (356)); and
applying solder balls to the ball contact pads Fig. 13H: solder balls (396) are coupled to ball contact pads/UBM (394); See ¶ [0152]).
However, Scanlan does not specifically disclose ball bumps.
In a similar field of endeavor, Kinsman discloses ball bumps (Fig. 1A shows ball bumps (20) deposited on bond pads (12) which are connected to IC chip (14)).
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the manufacturing process disclosed by Scanlan to include features disclosed by Kinsman to use ball bumping using conventional wire bonding tools to reduce costs (Kinsman, ¶ [0005]) in order to create an improved method for forming a chip scale package that does not significantly complicate the manufacturing or handling of the integrated circuitry and that is repeatable and reliable when using conventional mass production manufacturing techniques (See Kinsman, ¶ [0011]).
Re: claim 16, the combination of Scanlan in view of Kinsman discloses all the limitations of claim 15 on which this claim depends.
Scanlan also discloses further comprising drilling vias in the overmold to the ball bumps on the IC chip (See ¶ [0141] … laser drilling, mechanical drilling, or other suitable process to form openings completely through insulating layer 388 to expose interconnects 356).
Re: claim 17, the combination of Scanlan in view of Kinsman discloses all the limitations of claim 15 on which this claim depends.
Scanlan also discloses further comprising:
drilling vias in the overmold to the ball bumps on the IC chip (See (¶ [0141); and
drawing trace lines from the ball contact pads to the vias of the IC chip (Figs. 13E and 13G: trace lines (390b); Fig. 13H: ball contact pads (394); See ¶ [0150]).
Re: claim 18, the combination of Scanlan in view of Kinsman discloses all the limitations of claim 15 on which this claim depends.
Scanlan also discloses further comprising:
drilling vias in the overmold to the ball bumps on the IC chip (See Figs. 13E-13G; ¶ [0150]); and
filling the vias with a conductive material (Fig. 13E: 390a and 390b; ¶ [0143]: Conductive layer 390 can be one or more layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable electrically conductive material).
Re: claim 19, the combination of Scanlan in view of Kinsman discloses all the limitations of claim 15 on which this claim depends.
Kinsman further discloses wherein the overmold has a sufficiently thin dimension so as to expose at least a portion of the ball bumps on the IC chip (¶ [0033]: “FIG. 2 depicts how encapsulant material 30 may be applied to both the active surface 14… but not to overfill same to the point of being level with the top surfaces of intermediate conductive elements 20... If completely covered, the upper ends of intermediate conductive elements 20 may be exposed by abrasive planarization, or the encapsulant material 30 selectively etched to expose the upper ends.” In other words, the overmold/encapsulant (30) is filled to a height where a portion of the ball bumps/conductive elements (20) on the IC remain exposed.).
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the manufacturing process disclosed by Scanlan to create an improved method for forming a chip scale package that does not significantly complicate the manufacturing or handling of the integrated circuitry and that is repeatable and reliable when using conventional mass production manufacturing techniques. (See Kinsman, ¶ [0011]).
Re: claim 20, the combination of Scanlan in view of Kinsman discloses all the limitations of claim 15 on which this claim depends.
Scanlan also discloses further comprising drawing trace lines from the ball contact pads to the ball bumps on the IC chip (Figs. 13E and 13G: trace lines (390b); Fig. 13H: ball contact pads (394); Figs. 13E and 13G: trace lines (390b) couple to ball bumps (356) on IC chip (334); ¶ [0053]: multiple dielectric layers and device interconnect traces, which may or may not be associated with the RDL, are formed in accordance with the principles described herein).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
BYUN (US 20110100689 A1) discloses similar structure included in applicants claims.
HAN et al. (US 10217873 B2) discloses similar structure included in applicants claims.
LYTEL (US 20090061564 A1) discloses similar structure included in applicants claims.
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/WILLIAM ADROVEL/Examiner, Art Unit 2898
/AJAY OJHA/Supervisory Patent Examiner, Art Unit 2898