DETAILED ACTION
Examiner Note
There are two sets of claims which appear to be the same. If the applicant intended to amend the claims, then they should be explicitly labeled as such. For prosecution purposes, the two sets of claims submitted on 09/29/2023 will be considered to be two copies of the same set of claims.
General Remarks
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
When responding to this office action, applicants are advised to provide the examiner with line numbers and page numbers in the application and/or references cited to assist the examiner in locating appropriate paragraphs.
Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
For Examiner’s Interview fill out the online Automated Interview Request (AIR) form (http://www.uspto.gov/patent/uspto-automated-interview-request-air-form.html).
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-2 and 4-7 are rejected under 35 U.S.C. 102(a)(1) and 35 U.S.C. 102(a)(2) as being anticipated by Kano (US 6008530), hereinafter “Kano.”
Re: Independent claim 1, Kano discloses an assembly (See Fig. 1: IC package) comprising:
an integrated circuit (IC) chip having IC contact terminals (Fig. 2: semiconductor chip 3, pins 2);
surface interfaces coupled to the IC chip (Fig. 2 shows surface interfaces/pins 2 coupled to IC chip 3), wherein at least one first surface interface and at least one second surface interface of the surface interfaces are configured to couple to a motherboard (Fig. 1 shows IC package with pins 2 on multiple surfaces; Also see Figs. 5 and 9; col. 3, lns. 32-34: by mounting terminals on two or more faces of the polyhedron, simultaneous connection to two or more printed circuit boards is made possible, i.e., configured to couple to a motherboard.); and
surface contact terminals on the surface interfaces (Fig. 1: pins 2), wherein the surface contact terminals couple to the IC contact terminals (Fig. 2: IC chip 3 couples to surface contact terminals 2), and wherein at least one subset of the surface contact terminals also couples to at least one subset of motherboard contact terminals on the motherboard (col. 3, lns. 32-34).
Re: claim 2, Kano discloses all the limitations of the assembly of claim 1.
Kano further discloses wherein the surface interfaces comprise six surface interfaces (See Fig. 1), and wherein the six surface interfaces form a cubic IC package (See Fig. 1; col. 3, lns. 25-26: It is further preferable that the hexahedron be an approximate cube).
Re: claim 4, Kano discloses all the limitations of the assembly of claim 1.
Kano further discloses wherein the surface interfaces form a cubic IC package (See Fig. 1), wherein solder balls are coupled to surface contact terminals on at least one surface interface of the cubic IC package (Fig. 1: pins 2), and wherein the solder balls enable the surface contact terminals coupled thereto to couple to the at least one subset of motherboard contact terminals (See Fig. 9 and col. 3, lns. 32-34; col. 7, lns. 21-24: The pins 2 are in connection with the pins that are in the high-density part that is in electrical connection with the printed circuit board mounting face…).
Re: claim 5, Kano discloses all the limitations of the assembly of claim 1.
Kano further discloses wherein the surface interfaces form a cubic IC package (Fig. 1), and wherein the cubic IC package is configured to be inserted at least partially into a cavity of the motherboard (Fig. 5 shows multiple IC packages (1) inserted into a cavity surrounded by optical input/output modules 201 and a surface of a substrate (202), i.e., motherboard.).
Re: claim 6, Kano discloses all the limitations of the assembly of claim 1.
Kano further discloses wherein at least five surface interfaces of the surface interfaces are configured to couple to the motherboard (Fig. 1 shows an IC package (1) with multiple surfaces; col. 10, lns. 12-14: Additionally, by means of terminals that are disposed on a plurality of faces, it is possible to mount a child board with a polyhedral IC package mounted to it to a mother board.; Also see Fig. 5), and wherein at least one subset of surface contact terminals on the at least five surface interfaces couples to the at least one subset of motherboard contact terminals (Fig. 5 shows IC packages 1 which are coupled to a board (202), i.e., motherboard.).
Re: claim 7, Kano discloses all the limitations of the assembly of claim 1.
Kano further discloses wherein at least one third surface interface of the surface interfaces is configured to couple to an auxiliary printed circuit board (PCB) (Fig. 9 shows a high-density multi-layer printed circuit board (81) coupled onto the IC package (1) with pins (2); col. 10, lns. 4-14: … electrical access is facilitated. Therefore, when performing inspection after mounting, it is possible to measure the electrical characteristics of the terminal... Additionally, by means of terminals that are disposed on a plurality of faces, it is possible to mount a child board with a polyhedral IC package mounted to it to a mother board.; In other words, electrical access to one of the surfaces, which is not connected to a motherboard, can allow access for testing such as measuring electrical characteristics of a terminal on IC package (1).).
Claim Rejections - 35 USC § 103
The following is a quotation of AIA 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim 3 is rejected under AIA 35 U.S.C. 103 as being unpatentable over Kano in view of Harney et al. (US 7040922 B2), hereinafter “Harney.”
Re: claim 3, Kano discloses all the limitations of the assembly of claim 1.
Kano discloses all of the limitations of claim 1 above. Kano further discloses wherein the conductive tracing couples to at least one subset of the surface contact terminals (Fig. 2 shows conductive leads (4) which couple to surface contact terminals (2); col. 7, lns 33-34: conductive leads (4) make connections between pins (2) and the semiconductor chip (3)), and wherein the conductive tracing enables the at least one subset of the surface contact terminals coupled thereto to couple to the at least one subset of motherboard contact terminals (See Figs. 5 and 9; col. 7, lns. 35-37: FIG. 9 shows the polyhedral IC package (13) of FIG. 7, this showing the condition of the IC package mounted to printed circuit boards).
While Kano discloses conductive leads (4) such as shown in Fig. 2, Kano does not specifically disclose further comprising conductive tracing on the surface interfaces.
In a similar field of endeavor, Harney discloses further comprising conductive tracing on the surface interfaces (Fig. 5 shows a mounting member 14; Fig. 6 shows surfaces (16) and interface surface (22); col. 3, lns. 65-66: traces on or in the mounting member 14; col. 6, lns. 6-7: the traces 28 illustratively are formed on the surface 16 of the mounting member 14).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date to have modified the device disclosed in Kano by using insulated traces embedded on the surface, as disclosed in Harney, in order to reduce the potential of shorting the traces (28) extending from the interconnects (27) (See Harney, col. 5, lns. 56-60).
Claims 8-9, 11-16, and 18-20 are rejected under AIA 35 U.S.C. 103 as being unpatentable over Kano in view of Borzabadi et al. (US 20090152653 A1), hereinafter “Borzabadi.”
Re: Independent claim 8, Kano discloses A system (See Fig. 1: IC package; col. 4, lns. 49-50: FIGS. 12(A) to 12(F) show one embodiment of a method for producing an IC package of the present invention) comprising:
obtaining an integrated circuit (IC) chip (Fig. 2: semiconductor chip 3, pins 2);
providing surface interfaces, wherein at least one first surface interface and at least one second surface interface of the surface interfaces are configured to couple to a motherboard (Fig. 1 shows IC package with pins 2 on multiple surfaces; Also see Figs. 5 and 9; col. 3, lns. 32-34: by mounting terminals on two or more faces of the polyhedron, simultaneous connection to two or more printed circuit boards is made possible, i.e., configured to couple to a motherboard.);
providing surface contact terminals on the surface interfaces (Fig. 1: pins 2);
coupling the surface contact terminals to IC contact terminals on the IC chip (Fig. 2: IC chip 3 couples to surface contact terminals 2), wherein at least one subset of the surface contact terminals also couples to at least one subset of motherboard contact terminals on the motherboard (col. 3, lns. 32-34); and
coupling the surface interfaces to the IC chip (Fig. 2 shows surface interfaces/pins (2) which are coupled to the IC chip (3) via conductive leads (4)).
However, Kano does not clearly disclose
one or more processors; and
logic encoded in one or more non-transitory computer-readable storage media for execution by the one or more processors and when executed operable to cause the one or more processors to perform operations comprising:
In a similar field of endeavor having to do with packaging chips inside of a cubic housing, Borzabadi discloses one or more processors (¶ [0020]: one or more processors); and
logic encoded in one or more non-transitory computer-readable storage media for execution by the one or more processors and when executed operable to cause the one or more processors to perform operations comprising (¶ [0020]: unique stored program instructions that control the one or more processors to implement all of the functions of MEMS packaging device):
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the instant application to have used a manufacturing process as described in Borzabadi to develop an encapsulated IC chip as claimed (See Borzabadi, ¶ [0020]) in order to create versatile packaging for enclosed devices such as IC chips (See Borzabadi, ¶ [0006]).
Re: claim 9, the combination of Kano and Borzabadi discloses all the limitations of the system of claim 8.
Kano further discloses wherein the surface interfaces comprise six surface interfaces (See Fig. 1), and wherein the six surface interfaces form a cubic IC package (See Fig. 1; col. 3, lns. 25-26: It is further preferable that the hexahedron be an approximate cube).
Re: claim 11, the combination of Kano and Borzabadi discloses all the limitations of the system of claim 8.
Kano further discloses wherein the surface interfaces form a cubic IC package (See Fig. 1), wherein solder balls are coupled to surface contact terminals on at least one surface interface of the cubic IC package (Fig. 1: pins 2), and wherein the solder balls enable the surface contact terminals coupled thereto to couple to the at least one subset of motherboard contact terminals (See Fig. 9 and col. 3, lns. 32-34; col. 7, lns. 21-24: The pins 2 are in connection with the pins that are in the high-density part that is in electrical connection with the printed circuit board mounting face…).
Re: claim 12, the combination of Kano and Borzabadi discloses all the limitations of the system of claim 8.
Kano further discloses wherein the surface interfaces form a cubic IC package (Fig. 1), and wherein the cubic IC package is configured to be inserted at least partially into a cavity of the motherboard (Fig. 5 shows multiple IC packages (1) inserted into a cavity surrounded by optical input/output modules 201 and a surface of a substrate (202), i.e., motherboard.).
Re: claim 13, the combination of Kano and Borzabadi discloses all the limitations of the system of claim 8.
Kano further discloses wherein at least five surface interfaces of the surface interfaces are configured to couple to the motherboard (Fig. 1 shows an IC package (1) with multiple surfaces; col. 10, lns. 12-14: Additionally, by means of terminals that are disposed on a plurality of faces, it is possible to mount a child board with a polyhedral IC package mounted to it to a mother board.; Also see Fig. 5), and wherein at least one subset of surface contact terminals on the at least five surface interfaces couples to the at least one subset of motherboard contact terminals (Fig. 5 shows IC packages 1 which are coupled to a board (202), i.e., motherboard.).
Re: claim 14, the combination of Kano and Borzabadi discloses all the limitations of the system of claim 8.
Kano further discloses wherein at least one third surface interface of the surface interfaces is configured to couple to an auxiliary printed circuit board (PCB) (Fig. 9 shows a high-density multi-layer printed circuit board (81) coupled onto the IC package (1) with pins (2); col. 10, lns. 4-14: … electrical access is facilitated. Therefore, when performing inspection after mounting, it is possible to measure the electrical characteristics of the terminal... Additionally, by means of terminals that are disposed on a plurality of faces, it is possible to mount a child board with a polyhedral IC package mounted to it to a mother board.; In other words, electrical access to one of the surfaces, which is not connected to a motherboard, can allow access for testing such as measuring electrical characteristics of a terminal on IC package (1).).
Re: Independent claim 15, Kano discloses A … method comprising (col. 4, lns. 49-50: FIGS. 12(A) to 12(F) show one embodiment of a method for producing an IC package of the present invention):
obtaining an integrated circuit (IC) chip (Fig. 2: semiconductor chip 3, pins 2);
providing surface interfaces, wherein at least one first surface interface and at least one second surface interface of the surface interfaces are configured to couple to a motherboard (Fig. 1 shows IC package with pins 2 on multiple surfaces; Also see Figs. 5 and 9; col. 3, lns. 32-34: by mounting terminals on two or more faces of the polyhedron, simultaneous connection to two or more printed circuit boards is made possible, i.e., configured to couple to a motherboard.);
providing surface contact terminals on the surface interfaces (Fig. 1: pins 2);
coupling the surface contact terminals to IC contact terminals on the IC chip (Fig. 2: IC chip 3 couples to surface contact terminals 2), wherein at least one subset of the surface contact terminals also couples to at least one subset of motherboard contact terminals on the motherboard (col. 3, lns. 32-34); and
coupling the surface interfaces to the IC chip (Fig. 2 shows surface interfaces/pins (2) which are coupled to the IC chip (3) via conductive leads (4)).
However, Kano does not specifically disclose a computer-implemented method.
In a similar field of endeavor having to do with packaging chips inside of a cubic housing, Borzabadi discloses a computer-implemented method (¶ [0020]: unique stored program instructions that control the one or more processors to implement all of the functions of MEMS packaging device).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the instant application to have used a manufacturing process as described in Borzabadi to develop an encapsulated IC chip as claimed (See Borzabadi, ¶ [0020]) in order to create versatile packaging for enclosed devices such as IC chips (See Borzabadi, ¶ [0006]).
Re: claim 16, the combination of Kano and Borzabadi discloses all the limitations of the method of claim 15.
Kano further discloses wherein the surface interfaces comprise six surface interfaces, and wherein the six surface interfaces form a cubic IC package (See Fig. 1; col. 3, lns. 25-26: It is further preferable that the hexahedron be an approximate cube).
Re: claim 18, the combination of Kano and Borzabadi discloses all the limitations of the method of claim 15.
Kano further discloses wherein the surface interfaces form a cubic IC package (See Fig. 1), wherein solder balls are coupled to surface contact terminals on at least one surface interface of the cubic IC package (Fig. 1: pins 2), and wherein the solder balls enable the surface contact terminals coupled thereto to couple to the at least one subset of motherboard contact terminals (See Fig. 9 and col. 3, lns. 32-34; col. 7, lns. 21-24: The pins 2 are in connection with the pins that are in the high-density part that is in electrical connection with the printed circuit board mounting face…).
Re: claim 19, the combination of Kano and Borzabadi discloses all the limitations of the method of claim 15.
Kano further discloses wherein the surface interfaces form a cubic IC package (Fig. 1), and wherein the cubic IC package is configured to be inserted at least partially into a cavity of the motherboard (Fig. 5 shows multiple IC packages (1) inserted into a cavity surrounded by optical input/output modules 201 and a surface of a substrate (202), i.e., motherboard.).
Re: claim 20, the combination of Kano and Borzabadi discloses all the limitations of the method of claim 15.
Kano further discloses wherein at least five surface interfaces of the surface interfaces are configured to couple to the motherboard (Fig. 1 shows an IC package (1) with multiple surfaces; col. 10, lns. 12-14: Additionally, by means of terminals that are disposed on a plurality of faces, it is possible to mount a child board with a polyhedral IC package mounted to it to a mother board.; Also see Fig. 5), and wherein at least one subset of surface contact terminals on the at least five surface interfaces couples to the at least one subset of motherboard contact terminals (Fig. 5 shows IC packages 1 which are coupled to a board (202), i.e., motherboard.).
Claims 10 and 17 are rejected under AIA 35 U.S.C. 103 as being unpatentable over Kano in view of Borzabadi, and further in view of Harney.
Re: claim 10, the combination of Kano in view of Borzabadi discloses all the limitations of the system of claim 8.
Kano further discloses wherein the conductive tracing couples to at least one subset of the surface contact terminals (Fig. 2 shows conductive leads (4) which couple to surface contact terminals (2); col. 7, lns 33-34: conductive leads (4) make connections between pins (2) and the semiconductor chip (3)), and wherein the conductive tracing enables the at least one subset of the surface contact terminals coupled thereto to couple to the at least one subset of motherboard contact terminals (See Figs. 5 and 9; col. 7, lns. 35-37: FIG. 9 shows the polyhedral IC package (13) of FIG. 7, this showing the condition of the IC package mounted to printed circuit boards).
While Kano discloses conductive leads (4) such as shown in Fig. 2, the combination of Kano in view of Borzabadi does not specifically disclose further comprising conductive tracing on the surface interfaces.
In a similar field of endeavor, Harney discloses further comprising conductive tracing on the surface interfaces (Fig. 5 shows a mounting member 14; Fig. 6 shows surfaces (16) and interface surface (22); col. 3, lns. 65-66: traces on or in the mounting member 14; col. 6, lns. 6-7: the traces 28 illustratively are formed on the surface 16 of the mounting member 14).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date to have modified the device disclosed in Kano by using insulated traces embedded on the surface, as disclosed in Harney, in order to reduce the potential of shorting the traces (28) extending from the interconnects (27) (See Harney, col. 5, lns. 56-60).
Re: claim 17, the combination of Kano in view of Borzabadi discloses all the limitations the method of claim 15.
Kano further discloses wherein the conductive tracing couples to at least one subset of the surface contact terminals (Fig. 2 shows conductive leads (4) which couple to surface contact terminals (2); col. 7, lns 33-34: conductive leads (4) make connections between pins (2) and the semiconductor chip (3)), and wherein the conductive tracing enables the at least one subset of the surface contact terminals coupled thereto to couple to the at least one subset of motherboard contact terminals (See Figs. 5 and 9; col. 7, lns. 35-37: FIG. 9 shows the polyhedral IC package (13) of FIG. 7, this showing the condition of the IC package mounted to printed circuit boards).
While Kano discloses conductive leads (4) such as shown in Fig. 2, the combination of Kano in view of Borzabadi does not specifically disclose further comprising conductive tracing on the surface interfaces.
In a similar field of endeavor, Harney discloses further comprising conductive tracing on the surface interfaces (Fig. 5 shows a mounting member 14; Fig. 6 shows surfaces (16) and interface surface (22); col. 3, lns. 65-66: traces on or in the mounting member 14; col. 6, lns. 6-7: the traces 28 illustratively are formed on the surface 16 of the mounting member 14).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date to have modified the device disclosed in Kano by using insulated traces embedded on the surface, as disclosed in Harney, in order to reduce the potential of shorting the traces (28) extending from the interconnects (27) (See Harney, col. 5, lns. 56-60).
Conclusion
Prior art made of record and not relied upon are considered pertinent to current application disclosure.
KIM (US 20120153450 A1) Discloses structural details similar to the claimed invention.
NAGAYA et al. (US 6710435 B2) Discloses structural details similar to the claimed invention.
MALEK et al. (US 9549464 B2) Discloses structural details similar to the claimed invention.
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/WILLIAM ADROVEL/Examiner, Art Unit 2898
/AJAY OJHA/Supervisory Patent Examiner, Art Unit 2898