DETAILED ACTION
Response to Arguments
Applicant’s arguments with respect to claim(s) 1, 8, and 15 have been considered but are moot based on the new grounds of rejection.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-7 are rejected under 35 U.S.C. 103 as being unpatentable over KANO (US 6008530, see previous office action), hereinafter “Kano,” in view of KANG et al. (US 7508061 B2), hereinafter “Kang.”
Re: Independent claim 1, Kano discloses an assembly (See Fig. 1: IC package) comprising:
an integrated circuit (IC) chip having IC contact terminals (Fig. 2: semiconductor chip 3, pins 2);
surface interfaces coupled to the IC chip (Fig. 2 shows surface interfaces/pins 2 coupled to IC chip 3), wherein at least one first surface interface and at least one second surface interface of the surface interfaces are configured to couple to a motherboard (Fig. 1 shows IC package with pins 2 on multiple surfaces; Also see Figs. 5 and 9; Fig. 5 shows coupling with at least two surfaces; col. 3, lns. 32-34: by mounting terminals on two or more faces of the polyhedron, simultaneous connection to two or more printed circuit boards is made possible, i.e., configured to couple to a motherboard.); and
surface contact terminals on the surface interfaces (Fig. 1: pins 2), wherein the surface contact terminals couple to the IC contact terminals (Fig. 2: IC chip 3 couples to surface contact terminals 2), …
…
While Kano discloses various examples of IC mounting on circuit boards, Kano does not clearly show wherein the motherboard comprises a cavity having walls, wherein one or more walls comprise motherboard contact terminals, and wherein at least one subset of the surface contact terminals also couples to at least one subset of motherboard contact terminals on the motherboard.
In a similar field of endeavor, Kang discloses wherein the motherboard comprises a cavity having walls, wherein one or more walls comprise motherboard contact terminals (Fig. 12; col. 3, lns. 19-22: three-dimensional semiconductor module having a multi-sided ground block; col. 4, lns. 23-28: plurality of ground terminals, ball grid array), and wherein at least one subset of the surface contact terminals also couples to at least one subset of motherboard contact terminals on the motherboard (Fig. 12 shows device 700 which connects to five sides of a socket 781; col. 4, lns. 23-28: plurality of ground terminals, ball grid array; col. 7, lns. 60-63: ground pad 784 and ground terminal 715).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the current application to have created a mounting cavity for a 3D semiconductor module wherein the mounting area of the semiconductor area may be reduced (See Kang, col. 1, lns. 60-62).
Re: claim 2, the combination of Kano in view of Kang discloses all the limitations of the assembly of claim 1.
Kano further discloses wherein the surface interfaces comprise six surface interfaces (See Fig. 1), and wherein the six surface interfaces form a cubic IC package (See Fig. 1; col. 3, lns. 25-26: It is further preferable that the hexahedron be an approximate cube).
Re: claim 3, the combination of Kano in view of Kang discloses all the limitations of the assembly of claim 1.
Kang also discloses further comprising conductive tracing on the surface interfaces (Fig. 12 shows traces on surface connecting to contact terminals 747), wherein the conductive tracing couples to at least one subset of the surface contact terminals (Fig. 12 shows traces on surface connecting to contact terminals 747), and wherein the conductive tracing enables the at least one subset of the surface contact terminals coupled thereto to couple to the at least one subset of motherboard contact terminals (Fig. 12 shows traces on surface connecting to contact terminals 747 which connect to Socket pins 783).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the current application to have created a mounting cavity for a 3D semiconductor module wherein the mounting area of the semiconductor area may be reduced (See Kang, col. 1, lns. 60-62).
Re: claim 4, the combination of Kano in view of Kang discloses all the limitations of the assembly of claim 1.
Kano further discloses wherein the surface interfaces form a cubic IC package (See Fig. 1), wherein solder balls are coupled to surface contact terminals on at least one surface interface of the cubic IC package (Fig. 1: pins 2), and wherein the solder balls enable the surface contact terminals coupled thereto to couple to the at least one subset of motherboard contact terminals (See Fig. 9 and col. 3, lns. 32-34; col. 7, lns. 21-24: The pins 2 are in connection with the pins that are in the high-density part that is in electrical connection with the printed circuit board mounting face…).
Re: claim 5, the combination of Kano in view of Kang discloses all the limitations of the assembly of claim 1.
Kang further discloses wherein the surface interfaces form a cubic IC package (Fig. 12), and wherein the cubic IC package is configured to be inserted at least partially into a cavity of the motherboard (Fig. 12 shows traces on surface connecting to contact terminals 747 which connect to Socket pins 783 of a motherboard 780).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the current application to have created a mounting cavity for a 3D semiconductor module wherein the mounting area of the semiconductor area may be reduced (See Kang, col. 1, lns. 60-62).
Re: claim 6, the combination of Kano in view of Kang discloses all the limitations of the assembly of claim 1.
Kang further discloses wherein at least five surface interfaces of the surface interfaces are configured to couple to the motherboard (Fig. 12 shows traces on surface connecting to contact terminals 747 which connect to Socket pins 783 which are on four walls of the socket and a fifth connection 784; col. 3, lns. 19-22: three-dimensional semiconductor module having a multi-sided ground block; col. 4, lns. 23-28: plurality of ground terminals, ball grid array), and wherein at least one subset of surface contact terminals on the at least five surface interfaces couples to the at least one subset of motherboard contact terminals (Fig. 12 shows traces on surface connecting to contact terminals 747 which connect to Socket pins 783 of the motherboard 780).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the current application to have created a mounting cavity for a 3D semiconductor module wherein the mounting area of the semiconductor area may be reduced (See Kang, col. 1, lns. 60-62).
Re: claim 7, the combination of Kano in view of Kang discloses all the limitations of the assembly of claim 1.
Kano further discloses wherein at least one third surface interface of the surface interfaces is configured to couple to an auxiliary printed circuit board (PCB) (Fig. 9 shows a high-density multi-layer printed circuit board (81) coupled onto the IC package (1) with pins (2); col. 10, lns. 4-14: … electrical access is facilitated. Therefore, when performing inspection after mounting, it is possible to measure the electrical characteristics of the terminal... Additionally, by means of terminals that are disposed on a plurality of faces, it is possible to mount a child board with a polyhedral IC package mounted to it to a mother board.; In other words, electrical access to one of the surfaces, which is not connected to a motherboard, can allow access for testing such as measuring electrical characteristics of a terminal on IC package (1).).
Claims 8-20 are rejected under 35 U.S.C. 103 as being unpatentable over KANO (US 6008530), in view of KANG et al. (US 7508061 B2), and further in view of Borzabadi et al. (US 20090152653 A1, see previous office action), hereinafter “Borzabadi.”
Re: Independent claim 8, Kano discloses a system comprising (See Fig. 1: IC package; col. 4, lns. 49-50: FIGS. 12(A) to 12(F) method for producing an IC package):
…
…
obtaining an integrated circuit (IC) chip (Fig. 2: semiconductor chip 3, pins 2);
providing surface interfaces, wherein at least one first surface interface and at least one second surface interface of the surface interfaces are configured to couple to a motherboard (Fig. 1 shows IC package with pins 2 on multiple surfaces; Fig. 5 shows coupling with at least two surfaces; Also Fig. 9; col. 3, lns. 32-34: by mounting terminals on two or more faces of the polyhedron, simultaneous connection to two or more printed circuit boards is made possible, i.e., configured to couple to a motherboard.);
providing surface contact terminals on the surface interfaces (Fig. 1: pins 2);
coupling the surface contact terminals to IC contact terminals on the IC chip (Fig. 2: IC chip 3 couples to surface contact terminals 2), …
coupling the surface interfaces to the IC chip (Fig. 2 shows surface interfaces/pins (2) which are coupled to the IC chip (3) via conductive leads (4)).
However, Kano does not clearly disclose
one or more processors; and
logic encoded in one or more non-transitory computer-readable storage media for execution by the one or more processors and when executed operable to cause the one or more processors to perform operations comprising:
wherein the motherboard comprises a cavity having walls, wherein one or more walls of the walls comprise motherboard contact terminals, and wherein at least one subset of the surface contact terminals also couples to at least one subset of motherboard contact terminals on the motherboard; and
In a similar field of endeavor, Kang discloses wherein the motherboard comprises a cavity having walls, wherein one or more walls of the walls comprise motherboard contact terminals (Fig. 12; col. 3, lns. 19-22: three-dimensional semiconductor module having a multi-sided ground block; col. 4, lns. 23-28: plurality of ground terminals, ball grid array), and wherein at least one subset of the surface contact terminals also couples to at least one subset of motherboard contact terminals on the motherboard (Fig. 12 shows device 700 which connects to five sides of a socket 781; col. 4, lns. 23-28: plurality of ground terminals, ball grid array; col. 7, lns. 60-63: ground pad 784 and ground terminal 715); and
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the current application to have created a mounting cavity for a 3D semiconductor module wherein the mounting area of the semiconductor area may be reduced (See Kang, col. 1, lns. 60-62).
However, the combination of Kano and Kang does not clearly disclose one or more processors; and logic encoded in one or more non-transitory computer-readable storage media for execution by the one or more processors and when executed operable to cause the one or more processors to perform operations comprising:
In a similar field of endeavor having to do with packaging chips inside of a cubic housing, Borzabadi discloses one or more processors (¶0020: one or more processors); and
logic encoded in one or more non-transitory computer-readable storage media for execution by the one or more processors and when executed operable to cause the one or more processors to perform operations comprising (¶0020: unique stored program instructions that control the one or more processors to implement all of the functions of MEMS packaging device):
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the instant application to have used a manufacturing process as described in Borzabadi to develop an encapsulated IC chip as claimed (See Borzabadi, ¶0020) in order to create versatile packaging for enclosed devices such as IC chips (See Borzabadi, ¶ [0006]).
Re: claim 9, the combination of Kano in view of Kang and Borzabadi discloses the system of claim 8.
Kano further discloses wherein the surface interfaces comprise six surface interfaces (See Fig. 1), and wherein the six surface interfaces form a cubic IC package (See Fig. 1; col. 3, lns. 25-26: It is further preferable that the hexahedron be an approximate cube).
Re: claim 10, the combination of Kano in view of Kang and Borzabadi discloses the system of claim 8.
Kang also discloses further comprising conductive tracing on the surface interfaces (Fig. 12 shows traces on surface connecting to contact terminals 747), wherein the conductive tracing couples to at least one subset of the surface contact terminals (Fig. 12 shows traces on surface connecting to contact terminals 747), and wherein the conductive tracing enables the at least one subset of the surface contact terminals coupled thereto to couple to the at least one subset of motherboard contact terminals (Fig. 12 shows traces on surface connecting to contact terminals 747 which connect to Socket pins 783).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the current application to have created a mounting cavity for a 3D semiconductor module wherein the mounting area of the semiconductor area may be reduced (See Kang, col. 1, lns. 60-62).
Re: claim 11, the combination of Kano in view of Kang and Borzabadi discloses the system of claim 8.
Kano further discloses wherein the surface interfaces form a cubic IC package (See Fig. 1), wherein solder balls are coupled to surface contact terminals on at least one surface interface of the cubic IC package (Fig. 1: pins 2), and wherein the solder balls enable the surface contact terminals coupled thereto to couple to the at least one subset of motherboard contact terminals (See Fig. 9 and col. 3, lns. 32-34; col. 7, lns. 21-24: The pins 2 are in connection with the pins that are in the high-density part that is in electrical connection with the printed circuit board mounting face…).
Re: claim 12, the combination of Kano in view of Kang and Borzabadi discloses the system of claim 8.
Kang further discloses wherein the surface interfaces form a cubic IC package (Fig. 12), and wherein the cubic IC package is configured to be inserted at least partially into a cavity of the motherboard (Fig. 12 shows traces on surface connecting to contact terminals 747 which connect to Socket pins 783 of a motherboard 780).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the current application to have created a mounting cavity for a 3D semiconductor module wherein the mounting area of the semiconductor area may be reduced (See Kang, col. 1, lns. 60-62).
Re: claim 13, the combination of Kano in view of Kang and Borzabadi discloses the system of claim 8.
Kang further discloses wherein at least five surface interfaces of the surface interfaces are configured to couple to the motherboard (Fig. 12 shows traces on surface connecting to contact terminals 747 which connect to Socket pins 783 which are on four walls of the socket and a fifth connection 784; col. 3, lns. 19-22: three-dimensional semiconductor module having a multi-sided ground block; col. 4, lns. 23-28: plurality of ground terminals, ball grid array), and wherein at least one subset of surface contact terminals on the at least five surface interfaces couples to the at least one subset of motherboard contact terminals (Fig. 12 shows traces on surface connecting to contact terminals 747 which connect to Socket pins 783 of the motherboard 780).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the current application to have created a mounting cavity for a 3D semiconductor module wherein the mounting area of the semiconductor area may be reduced (See Kang, col. 1, lns. 60-62).
Re: claim 14, the combination of Kano in view of Kang and Borzabadi discloses the system of claim 8.
Kano further discloses wherein at least one third surface interface of the surface interfaces is configured to couple to an auxiliary printed circuit board (PCB) (Fig. 9 shows a high-density multi-layer printed circuit board (81) coupled onto the IC package (1) with pins (2); col. 10, lns. 4-14: … electrical access is facilitated. Therefore, when performing inspection after mounting, it is possible to measure the electrical characteristics of the terminal... Additionally, by means of terminals that are disposed on a plurality of faces, it is possible to mount a child board with a polyhedral IC package mounted to it to a mother board.; In other words, electrical access to one of the surfaces, which is not connected to a motherboard, can allow access for testing such as measuring electrical characteristics of a terminal on IC package (1).).
Re: Independent claim 15, Kano discloses a … method comprising (col. 4, lns. 49-50: FIGS. 12(A) to 12(F) show one embodiment of a method for producing an IC package of the present invention):
obtaining an integrated circuit (IC) chip (Fig. 2: semiconductor chip 3, pins 2);
providing surface interfaces, wherein at least one first surface interface and at least one second surface interface of the surface interfaces are configured to couple to a motherboard (Fig. 1 shows IC package with pins 2 on multiple surfaces; Also see Figs. 5 and 9; col. 3, lns. 32-34: by mounting terminals on two or more faces of the polyhedron, simultaneous connection to two or more printed circuit boards is made possible, i.e., configured to couple to a motherboard.);
providing surface contact terminals on the surface interfaces (Fig. 1: pins 2);
coupling the surface contact terminals to IC contact terminals on the IC chip (Fig. 2: IC chip 3 couples to surface contact terminals 2), …
coupling the surface interfaces to the IC chip (Fig. 2 shows surface interfaces/pins (2) which are coupled to the IC chip (3) via conductive leads (4)).
However, Kano does not clearly disclose a computer-implemented …
wherein the motherboard comprises a cavity having walls, wherein one or more walls of the walls comprise motherboard contact terminals, and wherein at least one subset of the surface contact terminals also couples to at least one subset of motherboard contact terminals on the motherboard; and
In a similar field of endeavor, Kang discloses wherein the motherboard comprises a cavity having walls, wherein one or more walls of the walls comprise motherboard contact terminals (Fig. 12; col. 3, lns. 19-22: three-dimensional semiconductor module having a multi-sided ground block; col. 4, lns. 23-28: plurality of ground terminals, ball grid array), and wherein at least one subset of the surface contact terminals also couples to at least one subset of motherboard contact terminals on the motherboard (Fig. 12 shows device 700 which connects to five sides of a socket 781; col. 4, lns. 23-28: plurality of ground terminals, ball grid array; col. 7, lns. 60-63: ground pad 784 and ground terminal 715); and
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the current application to have created a mounting cavity for a 3D semiconductor module wherein the mounting area of the semiconductor area may be reduced (See Kang, col. 1, lns. 60-62).
However, the combination of Kano in view of Kang does not specifically disclose computer-implemented …
In a similar field of endeavor having to do with packaging chips inside of a cubic housing, Borzabadi discloses a computer-implemented … (¶0020: unique stored program instructions that control the one or more processors to implement all of the functions of MEMS packaging device).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the instant application to have used a manufacturing process as described in Borzabadi to develop an encapsulated IC chip as claimed (See Borzabadi, ¶ [0020]) in order to create versatile packaging for enclosed devices such as IC chips (See Borzabadi, ¶ [0006]).
Re: claim 16, the combination of Kano in view of Kang and Borzabadi discloses the method of claim 15.
Kano further discloses wherein the surface interfaces comprise six surface interfaces (See Fig. 1), and wherein the six surface interfaces form a cubic IC package (See Fig. 1; col. 3, lns. 25-26: It is further preferable that the hexahedron be an approximate cube).
Re: claim 17, the combination of Kano in view of Kang and Borzabadi discloses the method of claim 15.
Kang also discloses further comprising coupling conductive tracing to the surface interfaces (Fig. 12 shows traces on surface connecting to contact terminals 747), wherein the conductive tracing couples to at least one subset of the surface contact terminals (Fig. 12 shows traces on surface connecting to contact terminals 747), and wherein the conductive tracing enables the at least one subset of the surface contact terminals coupled thereto to couple to the at least one subset of motherboard contact terminals (Fig. 12 shows traces on surface connecting to contact terminals 747 which connect to Socket pins 783).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the current application to have created a mounting cavity for a 3D semiconductor module wherein the mounting area of the semiconductor area may be reduced (See Kang, col. 1, lns. 60-62).
Re: claim 18, the combination of Kano in view of Kang and Borzabadi discloses the method of claim 15.
Kano further discloses wherein the surface interfaces form a cubic IC package (See Fig. 1), wherein solder balls are coupled to surface contact terminals on at least one surface interface of the cubic IC package (Fig. 1: pins 2), and wherein the solder balls enable the surface contact terminals coupled thereto to couple to the at least one subset of motherboard contact terminals (See Fig. 9 and col. 3, lns. 32-34; col. 7, lns. 21-24: The pins 2 are in connection with the pins that are in the high-density part that is in electrical connection with the printed circuit board mounting face…).
Re: claim 19, the combination of Kano in view of Kang and Borzabadi discloses the method of claim 15.
Kang further discloses wherein the surface interfaces form a cubic IC package (Fig. 12), and wherein the cubic IC package is configured to be inserted at least partially into a cavity of the motherboard (Fig. 12 shows traces on surface connecting to contact terminals 747 which connect to Socket pins 783 of a motherboard 780).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the current application to have created a mounting cavity for a 3D semiconductor module wherein the mounting area of the semiconductor area may be reduced (See Kang, col. 1, lns. 60-62).
Re: claim 20, the combination of Kano in view of Kang and Borzabadi discloses the method of claim 15.
Kang further discloses wherein at least five surface interfaces of the surface interfaces are configured to couple to the motherboard (Fig. 12 shows traces on surface connecting to contact terminals 747 which connect to Socket pins 783 which are on four walls of the socket and a fifth connection 784; col. 3, lns. 19-22: three-dimensional semiconductor module having a multi-sided ground block; col. 4, lns. 23-28: plurality of ground terminals, ball grid array), and wherein at least one subset of surface contact terminals on the at least five surface interfaces couples to the at least one subset of motherboard contact terminals (Fig. 12 shows traces on surface connecting to contact terminals 747 which connect to Socket pins 783 of the motherboard 780).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the current application to have created a mounting cavity for a 3D semiconductor module wherein the mounting area of the semiconductor area may be reduced (See Kang, col. 1, lns. 60-62).
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to WILLIAM ADROVEL whose telephone number is (571)272-3048. The examiner can normally be reached 7:30 AM - 5:00 PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, LEONARD CHANG can be reached at (571) 270-3691. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/WILLIAM ADROVEL/Examiner, Art Unit 2898
/Leonard Chang/Supervisory Patent Examiner, Art Unit 2898
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