DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-6, 9-11, 13-17, and 19-20 are pending in this office action and presented for examination. Claims 1-2, 9, 13-14, 16, and 19 are newly amended, and claims 7-8, 12, and 18 are newly cancelled, by the response received August 19, 2026.
Examiner notes that in FIG. 2, a space is present before the number in “Even = 0” but is not present before the number in “Odd =1”.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-6, 9-11, 13-17, and 19-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites the limitation “the hardware execution circuitry to execute the decoded instruction according to the opcode” in lines 6-7. However, this limitation has insufficient antecedent basis in the claims. In addition, it is unclear as to whether the apparatus is being recited to comprise the execution circuitry.
Claim 1 recites the limitation “slot polarity is defined” in line 9. However, it is indefinite as to whether the slot polarity of this limitation is the same as, or different from, the slot polarity of the limitation “checking slot polarity” in claim 1, line 9.
Claim 1 recites the limitation “a slot” in lines 9-10. However, it is indefinite as to whether this slot is the same as, or different from, “memory allocation slot” of claim 1, line 8.
Claims 2-6 and 9-11 are rejected for failing to alleviate the rejections of claim 1 above.
Claim 2 recites the limitation “memory safety check” in line 2. However, it is indefinite as to whether this memory safety check is the same as, or different from, “a memory safety check” as recited in claim 1, line 4.
Claim 13 recites the limitation “slot polarity is defined” in line 8. However, it is indefinite as to whether the slot polarity of this limitation is the same as, or different from, the slot polarity of the limitation “checking slot polarity” in claim 13, line 8.
Claim 13 recites the limitation “a slot” in lines 8-9. However, it is indefinite as to whether this slot is the same as, or different from, “memory allocation slot” of claim 13, line 7.
Claims 14-17 are rejected for failing to alleviate the rejections of claim 13 above.
Claim 19 recites the limitation “the hardware execution circuitry to execute the decoded instruction according to the opcode” in lines 8-9. However, this limitation has insufficient antecedent basis in the claims. In addition, it is unclear as to whether the processor is being recited to comprise the execution circuitry.
Claim 19 recites the limitation “slot polarity is defined” in line 11. However, it is indefinite as to whether the slot polarity of this limitation is the same as, or different from, the slot polarity of the limitation “checking slot polarity” in claim 19, line 11.
Claim 19 recites the limitation “a slot” in lines 11-12. However, it is indefinite as to whether this slot is the same as, or different from, “memory allocation slot” of claim 19, line 10.
Claim 20 is rejected for failing to alleviate the rejections of claim 19 above.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-2, 4, 6, 9-11, 13-15, 17, and 19-20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Abhishek Raja et al. (Raja) (US 11221951 B1).
Consider claim 1, Raja discloses an apparatus (col. 17, lines 37-38, data processing apparatus) comprising: hardware decoder circuitry to decode an instruction into a decoded instruction (col. 17, line 44, the instruction decoder 6 decodes instructions), the instruction having an opcode to indicate hardware execution circuitry is to use metadata and instruction encodings to selectively perform a memory safety check; and the hardware execution circuitry to execute the decoded instruction according to the opcode (col. 15, lines 1-24, in some implementations, all memory access operations may by definition be considered to be tag-checked memory access operations. In other implementations it may be possible to define tag-checked memory access operations and non-tag-checked memory access operations. The non-tag-checked memory access operations are those memory access operations for which there is no architectural requirement to perform a tag check, while the tag-checked memory access operations are memory access operations for which a tag check is architecturally required (although at a micro-architectural level it is still possible to skip the tag check for a tag-checked load operation when the tag-check-skip conditions are determined to be satisfied, as described above). The tag-checked memory access operations could be distinguished from non-tag-checked memory access operations in different ways. In some cases, memory access instructions may have an encoding which signals whether the corresponding memory access operation should be processed as a tag-checked memory access operation or a non-tag-checked memory access operation. For example, a different opcode could be allocated for tag-checked memory accesses compared to non-tag-checked memory accesses, or another field in the instruction encoding could specify whether the tag-check is architecturally required; col. 17, lines 56-59, the processing circuitry also includes a memory access unit (or load/store unit) 15; col. 3, lines 38-55, one approach for protecting against certain memory usage errors of the types discussed above involves providing guard tags which are stored in a memory system in association with blocks of one or more memory system locations. Memory access circuitry may perform a memory access operation to access data stored in the memory system. Tag checking circuitry may perform at least one tag check for a tag-checked memory access operation for accessing data stored at one or more address memory system locations identified based on a target address specified by the tag-checked memory access operation. The target address is associated with an address tag. Each tag check comprises: determining whether the address tag associated with the target address corresponds to a guard tag stored in the memory system associated with at least a subset of the one or more addressed memory system locations, and performing an error reporting action when the tag check identifies that the address tag and the guard tag do not correspond); wherein the metadata includes a tag per memory allocation slot (col. 18, lines 55-56, address tag 40 (which is associated with the target address 42 identifying the addressed location 44 to be accessed)), the memory safety check includes checking slot polarity (col. 19, lines 17-29, hence, when a tag-guarded memory access is performed, the load/store unit 15 compares the address tag 40 and the guard tag 32 associated with a block 30 including the addressed location 44 and determines whether they match. The load/store unit 15 generates a match indication indicating whether the address tag 40 and the guard tag 32 matched. For example, this match indication could be a fault signal 60 which is generated if there is a mismatch between the address tag 40 and the guard tag 32, or an indication placed in a status register indicating whether there was a match, or an entry added to an error report to indicate the target address for which the error was detected and/or the instruction address of the instruction which triggered the error), and slot polarity is defined in terms of whether a slot is even or odd (col. 19, lines 17-29, hence, when a tag-guarded memory access is performed, the load/store unit 15 compares the address tag 40 and the guard tag 32 associated with a block 30 including the addressed location 44 and determines whether they match. The load/store unit 15 generates a match indication indicating whether the address tag 40 and the guard tag 32 matched. For example, this match indication could be a fault signal 60 which is generated if there is a mismatch between the address tag 40 and the guard tag 32, or an indication placed in a status register indicating whether there was a match, or an entry added to an error report to indicate the target address for which the error was detected and/or the instruction address of the instruction which triggered the error; for example, a bit of a tag or a match indication being a signal or bit which is a zero or a one corresponds to a slot being even or odd).
Consider claim 2, Raja discloses the apparatus of claim 1 (see above), wherein memory safety check includes loading and checking the metadata (col. 3, lines 38-55, one approach for protecting against certain memory usage errors of the types discussed above involves providing guard tags which are stored in a memory system in association with blocks of one or more memory system locations. Memory access circuitry may perform a memory access operation to access data stored in the memory system. Tag checking circuitry may perform at least one tag check for a tag-checked memory access operation for accessing data stored at one or more address memory system locations identified based on a target address specified by the tag-checked memory access operation. The target address is associated with an address tag. Each tag check comprises: determining whether the address tag associated with the target address corresponds to a guard tag stored in the memory system associated with at least a subset of the one or more addressed memory system locations, and performing an error reporting action when the tag check identifies that the address tag and the guard tag do not correspond).
Consider claim 4, Raja discloses the apparatus of claim 1 (see above), wherein the metadata is physically indexed (col. 18, lines 17-20, the guard tags associated with a certain number of blocks 30 can be gathered together and stored either within a different architecturally accessible memory location 34 within the physical address space).
Consider claim 6, Raja discloses the apparatus of claim 1 (see above), wherein the metadata is non-redundant (FIG. 2, tag storage locations 34).
Consider claim 9, Raja discloses the apparatus of claim 1 (see above), wherein a plurality of memory allocation slots are to be grouped into a first cluster and a plurality of tags are to be grouped into a second cluster (FIG. 2, for example, which shows the plurality of memory allocation slots grouped into a first cluster and the plurality of tags grouped into a second cluster).
Consider claim 10, Raja discloses the apparatus of claim 9 (see above), wherein memory allocation slots grouped into the first cluster are to be contiguous (FIG. 2, for example, which shows memory allocation slots grouped into the first cluster are contiguous).
Consider claim 11, Raja discloses the apparatus of claim 10 (see above), wherein tags grouped into the second cluster are to be contiguous (FIG. 2, for example, which shows tags grouped into the second cluster are contiguous).
Consider claim 13, Raja discloses a method comprising: decoding, by decoder circuitry, an instruction into a decoded instruction (col. 17, line 44, the instruction decoder 6 decodes instructions), the instruction having an opcode to indicate execution circuitry is to use metadata and instruction encodings to selectively perform a memory safety check; and executing, by the execution circuitry, the decoded instruction according to the opcode (col. 15, lines 1-24, in some implementations, all memory access operations may by definition be considered to be tag-checked memory access operations. In other implementations it may be possible to define tag-checked memory access operations and non-tag-checked memory access operations. The non-tag-checked memory access operations are those memory access operations for which there is no architectural requirement to perform a tag check, while the tag-checked memory access operations are memory access operations for which a tag check is architecturally required (although at a micro-architectural level it is still possible to skip the tag check for a tag-checked load operation when the tag-check-skip conditions are determined to be satisfied, as described above). The tag-checked memory access operations could be distinguished from non-tag-checked memory access operations in different ways. In some cases, memory access instructions may have an encoding which signals whether the corresponding memory access operation should be processed as a tag-checked memory access operation or a non-tag-checked memory access operation. For example, a different opcode could be allocated for tag-checked memory accesses compared to non-tag-checked memory accesses, or another field in the instruction encoding could specify whether the tag-check is architecturally required; col. 17, lines 56-59, the processing circuitry also includes a memory access unit (or load/store unit) 15; col. 3, lines 38-55, one approach for protecting against certain memory usage errors of the types discussed above involves providing guard tags which are stored in a memory system in association with blocks of one or more memory system locations. Memory access circuitry may perform a memory access operation to access data stored in the memory system. Tag checking circuitry may perform at least one tag check for a tag-checked memory access operation for accessing data stored at one or more address memory system locations identified based on a target address specified by the tag-checked memory access operation. The target address is associated with an address tag. Each tag check comprises: determining whether the address tag associated with the target address corresponds to a guard tag stored in the memory system associated with at least a subset of the one or more addressed memory system locations, and performing an error reporting action when the tag check identifies that the address tag and the guard tag do not correspond); wherein the metadata includes a tag per memory allocation slot (col. 18, lines 55-56, address tag 40 (which is associated with the target address 42 identifying the addressed location 44 to be accessed)), the memory safety check includes checking slot polarity (col. 19, lines 17-29, hence, when a tag-guarded memory access is performed, the load/store unit 15 compares the address tag 40 and the guard tag 32 associated with a block 30 including the addressed location 44 and determines whether they match. The load/store unit 15 generates a match indication indicating whether the address tag 40 and the guard tag 32 matched. For example, this match indication could be a fault signal 60 which is generated if there is a mismatch between the address tag 40 and the guard tag 32, or an indication placed in a status register indicating whether there was a match, or an entry added to an error report to indicate the target address for which the error was detected and/or the instruction address of the instruction which triggered the error), and slot polarity is defined in terms of whether a slot is even or odd (col. 19, lines 17-29, hence, when a tag-guarded memory access is performed, the load/store unit 15 compares the address tag 40 and the guard tag 32 associated with a block 30 including the addressed location 44 and determines whether they match. The load/store unit 15 generates a match indication indicating whether the address tag 40 and the guard tag 32 matched. For example, this match indication could be a fault signal 60 which is generated if there is a mismatch between the address tag 40 and the guard tag 32, or an indication placed in a status register indicating whether there was a match, or an entry added to an error report to indicate the target address for which the error was detected and/or the instruction address of the instruction which triggered the error; for example, a bit of a tag or a match indication being a signal or bit which is a zero or a one corresponds to a slot being even or odd).
Consider claim 14, Raja discloses the method of claim 13 (see above), wherein the memory safety check includes loading and checking the metadata (col. 3, lines 38-55, one approach for protecting against certain memory usage errors of the types discussed above involves providing guard tags which are stored in a memory system in association with blocks of one or more memory system locations. Memory access circuitry may perform a memory access operation to access data stored in the memory system. Tag checking circuitry may perform at least one tag check for a tag-checked memory access operation for accessing data stored at one or more address memory system locations identified based on a target address specified by the tag-checked memory access operation. The target address is associated with an address tag. Each tag check comprises: determining whether the address tag associated with the target address corresponds to a guard tag stored in the memory system associated with at least a subset of the one or more addressed memory system locations, and performing an error reporting action when the tag check identifies that the address tag and the guard tag do not correspond).
Consider claim 15, Raja discloses the method of claim 13 (see above), wherein the metadata is linearly indexed or physically indexed (col. 18, lines 17-20, the guard tags associated with a certain number of blocks 30 can be gathered together and stored either within a different architecturally accessible memory location 34 within the physical address space).
Consider claim 17, Raja discloses the method of claim 13 (see above), wherein the metadata is to include a plurality of contiguous tags corresponding to a plurality of contiguous memory allocation slots (col. 18, lines 55-56, address tag 40 (which is associated with the target address 42 identifying the addressed location 44 to be accessed); FIG. 2, for example, which shows the plurality of memory allocation slots grouped into a first cluster and the plurality of tags grouped into a second cluster; FIG. 2, for example, which shows memory allocation slots grouped into the first cluster are contiguous; FIG. 2, for example, which shows tags grouped into the second cluster are contiguous).
Consider claim 19, Raja discloses a system comprising: a memory (col. 8, line 11, memory system) to store data (col. 3, line 43, data stored in the memory system) and metadata (col. 18, line 17, guard tags); and a processor (col. 19, line 66, processor 2) including: hardware decoder circuitry to decode an instruction into a decoded instruction (col. 17, line 44, the instruction decoder 6 decodes instructions), the instruction having an opcode to indicate hardware execution circuitry is to use the metadata and instruction encodings to selectively perform a memory safety check; and the hardware execution circuitry to execute the decoded instruction according to the opcode (col. 15, lines 1-24, in some implementations, all memory access operations may by definition be considered to be tag-checked memory access operations. In other implementations it may be possible to define tag-checked memory access operations and non-tag-checked memory access operations. The non-tag-checked memory access operations are those memory access operations for which there is no architectural requirement to perform a tag check, while the tag-checked memory access operations are memory access operations for which a tag check is architecturally required (although at a micro-architectural level it is still possible to skip the tag check for a tag-checked load operation when the tag-check-skip conditions are determined to be satisfied, as described above). The tag-checked memory access operations could be distinguished from non-tag-checked memory access operations in different ways. In some cases, memory access instructions may have an encoding which signals whether the corresponding memory access operation should be processed as a tag-checked memory access operation or a non-tag-checked memory access operation. For example, a different opcode could be allocated for tag-checked memory accesses compared to non-tag-checked memory accesses, or another field in the instruction encoding could specify whether the tag-check is architecturally required; col. 17, lines 56-59, the processing circuitry also includes a memory access unit (or load/store unit) 15; col. 3, lines 38-55, one approach for protecting against certain memory usage errors of the types discussed above involves providing guard tags which are stored in a memory system in association with blocks of one or more memory system locations. Memory access circuitry may perform a memory access operation to access data stored in the memory system. Tag checking circuitry may perform at least one tag check for a tag-checked memory access operation for accessing data stored at one or more address memory system locations identified based on a target address specified by the tag-checked memory access operation. The target address is associated with an address tag. Each tag check comprises: determining whether the address tag associated with the target address corresponds to a guard tag stored in the memory system associated with at least a subset of the one or more addressed memory system locations, and performing an error reporting action when the tag check identifies that the address tag and the guard tag do not correspond); wherein the metadata includes a tag per memory allocation slot (col. 18, lines 55-56, address tag 40 (which is associated with the target address 42 identifying the addressed location 44 to be accessed)), the memory safety check includes checking slot polarity (col. 19, lines 17-29, hence, when a tag-guarded memory access is performed, the load/store unit 15 compares the address tag 40 and the guard tag 32 associated with a block 30 including the addressed location 44 and determines whether they match. The load/store unit 15 generates a match indication indicating whether the address tag 40 and the guard tag 32 matched. For example, this match indication could be a fault signal 60 which is generated if there is a mismatch between the address tag 40 and the guard tag 32, or an indication placed in a status register indicating whether there was a match, or an entry added to an error report to indicate the target address for which the error was detected and/or the instruction address of the instruction which triggered the error), and slot polarity is defined in terms of whether a slot is even or odd (col. 19, lines 17-29, hence, when a tag-guarded memory access is performed, the load/store unit 15 compares the address tag 40 and the guard tag 32 associated with a block 30 including the addressed location 44 and determines whether they match. The load/store unit 15 generates a match indication indicating whether the address tag 40 and the guard tag 32 matched. For example, this match indication could be a fault signal 60 which is generated if there is a mismatch between the address tag 40 and the guard tag 32, or an indication placed in a status register indicating whether there was a match, or an entry added to an error report to indicate the target address for which the error was detected and/or the instruction address of the instruction which triggered the error; for example, a bit of a tag or a match indication being a signal or bit which is a zero or a one corresponds to a slot being even or odd).
Consider claim 20, Raja discloses the system of claim 19 (see above), wherein the metadata is to include a plurality of contiguous tags corresponding to a plurality of contiguous memory allocation slots (col. 18, lines 55-56, address tag 40 (which is associated with the target address 42 identifying the addressed location 44 to be accessed); FIG. 2, for example, which shows the plurality of memory allocation slots grouped into a first cluster and the plurality of tags grouped into a second cluster; FIG. 2, for example, which shows memory allocation slots grouped into the first cluster are contiguous; FIG. 2, for example, which shows tags grouped into the second cluster are contiguous) for data (col. 3, line 43, data stored in the memory system).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 3 is/are rejected under 35 U.S.C. 103 as being unpatentable over Raja as applied to claim 1 above, and further in view of Parker et al. (Parker) (US 20200218673 A1).
Consider claim 3, Raja discloses the apparatus of claim 1 (see above). However, Raja does not explicitly disclose that the metadata is linearly indexed.
On the other hand, Parker discloses linear indexing ([0328], lines 2-4, in a linear table, a required entry for a given address can be accessed by a single index into the table structure; [0328], lines 10-11, linear index).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Parker with the invention of Raja for fast performance (Parker, [0328], line 11). Note that Parker’s teaching, when applied to the invention of Raja which entails stored metadata, results in the overall claimed limitation.
Claim(s) 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Raja as applied to claim 1 above, and further in view of Pattabiraman et al. (Pattabiraman) (US 20080140962 A1).
Consider claim 5, Raja discloses the apparatus of claim 1 (see claim 1), but does not disclose the metadata is redundant.
On the other hand, Pattabiraman discloses redundant metadata ([0074], lines 17-20, in addition, a redundant copy of the metadata may be stored in a separate hash table in a protected heap region, which can then be used to restore the metadata in case it is corrupted).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Pattabiraman with the invention of Rajain order to counteract the effects of metadata corruption.
Claim(s) 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Raja as applied to claim 13 above, and further in view of LeMay et al. (LeMay) (US 20210096872 A1).
Consider claim 16, Raja discloses the method of claim 13 (see above), but does not disclose eliding, by a compiler, unneeded checks.
On the other hand, LeMay discloses eliding, by a compiler, unneeded checks ([0027], lines 4-7, certain security checks (e.g., to enforce memory safety checks or type safety checks) may be elided (e.g., by a compiler) using static analysis).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of LeMay with the invention of Raja in order to forgo unnecessary additional overhead (LeMay, [0027], lines 12-14).
Response to Arguments
Applicant on page 7 argues: “Applicant amends the specification at paragraphs 7, 8, 57, 60, 69, 73, 74, and 76. Accordingly, Applicant requests withdrawal of the objections to the specification.”
In view of the aforementioned amendments, the previously presented objections to the specification are withdrawn.
Applicant on page 8 argues: “The Applicant amends Figures 1-10. Accordingly, the Applicant requests withdrawal of the objections to Figures 1-10.”
In view of the aforementioned amendments, the previously presented objections to the drawings are withdrawn.
Applicant on page 8 argues: “In response, independent claims 1 and 19 have been amended to advance prosecution without conceding to these rejections.”
In view of the aforementioned amendments, the previously presented rejections under 35 USC 101 are withdrawn.
Applicant on page 9 argues: ‘Regarding the rejections of independent claims 1 and 19, antecedent basis for "the execution circuitry" is found in line 3 of claim 1 and line 5 of claim 19 respectively.’
However, while antecedent basis for “the execution circuitry” is found in claim 1, line 3, there does not appear to be antecedent basis for “hardware execution circuitry to execute the decoded instruction according to the opcode” in particular. In addition, it remains unclear as to whether the apparatus is being recited to comprise the execution circuitry. In general, it is unclear as to whether “the hardware execution circuitry to execute the decoded instruction according to the opcode” is intended to recite a further element of the apparatus (in view of, for example, the “and” in claim 1, line 5) or further narrow the previously recited hardware execution circuitry (despite the presence of “and” language and the lack of “wherein … is to…” language, for example). If Applicant intends for both possibilities to be the case, Examiner recommends reciting language akin to “and the hardware execution circuitry, wherein the hardware execution circuitry is to execute…”.
The response to arguments in the preceding paragraph are likewise applicable to the analogous arguments directed to analogous claim 19.
Applicant on page 9 argues: “In response to the rejections of claims 2, 14, and 16, these claims have been amended to advance prosecution without conceding to the rejections.”
In view of the aforementioned amendments, the corresponding indefinite rejections of claims 2, 14, and 16 are withdrawn.
Applicant on page 9 argues: “Claims 7, 8, and 12 have been cancelled to advance prosecution without conceding to the rejection.”
In view of the aforementioned amendments, the corresponding indefinite rejections of claims 7, 8, and 12 are withdrawn.
Applicant across pages 9-10 argues: “In response, to advance prosecution without conceding to the rejections, independent claims 1, 13, and 19 have been amended such that none of the cited references, taken alone or in combination, disclose or suggest the claimed recitations when taken in the context of the claims as a whole. For example, independent claim 1 includes at least one limitation not disclosed or suggested by any of the cited references, alone or combined; specifically, that the metadata includes a tag per memory allocation slot, the memory safety check includes checking slot polarity, and slot polarity is defined in terms of whether a slot is even or odd. Support for these amendments may be found at least in original claims 8 and 12, paragraph 0057, and Figure 2. Each of the other claims includes a corresponding limitation by amendment or dependence. Without conceding to the examiner's rejections of claims 8, 12, and 18 based on col. 18 lines 55-56 and col. 19 lines 17-29 of Raja, a memory safety check including checking slot polarity in not found in or suggested by those lines, anywhere else in Raja, or any of the other cited references.”
However, Raja appears to teach the amended claim language under the broadest reasonable interpretation of the amended claim language; see the Claim Rejections - 35 USC § 102 section above.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/KEITH E VICARY/Primary Examiner, Art Unit 2183
Prosecution Insights