DETAILED ACTION
This Office Action is in response to Application filed on September 29, 2023.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicants’ election without traverse of Invention I drawn to a method as recited in claim 1 and drawn to the embodiments shown in Figs. 6A-6G, claims 1-14, and canceled claims 15-30, in the reply filed on June 18, 2026 is acknowledged.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the Zener diodes recited in claims 9-11 must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
The drawings are objected to because the limitation “wherein the individual semiconductor dies are free from a backside metal coating” as stated in claim 13, and the limitation “wherein prior to performing the wafer dicing, no backside thinning is performed” as stated in claim 14, are not shown in the method illustrated by Figs. 6A-6G.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
The disclosure is objected to because of the following informalities:
Element 661 in Figs. 6A-6G should be labeled as “isolation trenches” instead of “backside coating”.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-14 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
The limitation “forming vertical diode devices coupled to one another in individual semiconductor dies on a semiconductor wafer” recited in claim 1 is rendered as indefinite because Applicants claim forming vertical diode devices on a semiconductor wafer, but the only feature formed on the semiconductor wafer (element 601) in Fig. 6B of current application is the stud bumps (element 665), which are not exactly vertical diode devices. It seems like the diode (elements 631 and 633) include the semiconductor wafer 601 rather than being formed on the semiconductor wafer 601.
Claim 1 is rendered as indefinite because it recites the term “individual semiconductor dies”. It is unclear why the semiconductor dies (elements 6051 and 6052) are referred to as “individual semiconductor dies” because they are formed on the same substrate, and therefore, are not individual. Furthermore, before the claimed wafer dicing step is performed, the alleged individual semiconductor dies share a common electrode or backside metal 659 in view of drawings of current application, and can be employed as a single semiconductor die without the claimed wafer dicing step rather than “individual semiconductor dies”, and therefore, it is not clear whether the “individual semiconductor dies” can share a common electrode or the “individual semiconductor dies” should include a plurality of corresponding electrodes.
Claims 2-14 depend on claim 1, and therefore, claims 2-14 are also indefinite.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 5, 7, and 9-14, as best understood, are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Lee et al. (US 20130264600 A1) hereinafter referred to as “Lee”.
Regarding claim 1, as best understood, Lee discloses a method (Figs. 4a-4c), comprising: forming vertical diode devices coupled to one another in individual semiconductor dies on a semiconductor wafer (30) having a device side surface and having an opposing backside surface; forming stud bumps (37b) on metal contacts (35b) ([0064]) coupled to the vertical diode devices on the device side surface; and performing wafer dicing to singulate the individual semiconductor dies from the semiconductor wafer (30) ([0102] and [0082]), the individual semiconductor dies including at least two of the vertical diode devices electrically coupled to one another by a semiconductor substrate (25) of the semiconductor wafer (30), the stud bumps (37b) forming terminals of the individual semiconductor dies.
Regarding claim 5, Lee discloses the method of claim 1, wherein forming vertical diode devices further comprises: forming a diffusion region (29) of a P-type or an N-type conductivity in the device side surface of a first epitaxial layer (27) of a conductivity type that is opposite the conductivity type of the diffusion region (29), wherein the first epitaxial layer (27) is formed over a semiconductor substrate (25) of a P-type or N-type conductivity that has the same conductivity type as the diffusion region (29), wherein the vertical diodes have a vertical P-N-P structure or a vertical N-P-N structure from the diffusion region (29), through the first epitaxial layer (27), and to the semiconductor substrate (25) ([0102] and [0063]).
Regarding claim 7, Lee discloses the method of claim 5, wherein the diffusion region (29) is a P-type diffusion region, the first epitaxial layer (27) is an N-type epitaxial layer, and the semiconductor substrate (25) is a P+type semiconductor substrate ([0102] and [0063]).
Regarding claim 9, Lee discloses the method of claim 5, where forming the vertical diode devices further comprises forming Zener diodes at a P-N junction between the first epitaxial layer (27) and the semiconductor substrate (25).
Regarding claim 10, Lee discloses the method of claim 9, wherein forming the stud bumps (37b) further comprises forming stud bumps (37b) that are coupled to cathodes of the Zener diodes.
Regarding claim 11, Lee discloses the method of claim 9, wherein forming the stud bumps (37a) further comprises forming stud bumps (37a) that are coupled to anodes of the Zener diodes.
Regarding claim 12, Lee discloses the method of claim 9, wherein forming the vertical diode devices further comprises forming a first vertical diode and a second vertical diode in the individual semiconductor dies, the first vertical diode coupled to a first one of the terminals (53a and 53b), the second vertical diode coupled to a second one of the terminals (53a and 53b) different from the first one of the terminals (53a and 53b).
Regarding claim 13, Lee discloses the method of claim 12, wherein the individual semiconductor dies are free from a backside metal coating (Fig. 4a-4c).
Regarding claim 14, Lee discloses the method of claim 13, wherein prior to performing the wafer dicing, no backside thinning is performed [0104].
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (US 20130264600 A1).
Regarding claim 8, Lee discloses the method of claim 5, wherein the diffusion region (29) is an N-type diffusion region, the first epitaxial layer (27) is a P-type epitaxial layer, and the semiconductor substrate (25) is an N+type semiconductor substrate ([0102] and [0063]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the n-type and p-type conductivity of the claimed regions or elements can be switched, because it has been a common practice in semiconductor industry to manufacture semiconductor devices with opposite conductivity types interchangeably by considering the availability and manufacturing cost of the doping mechanisms and source materials since switching conductivity types of two or more semiconductor regions or elements only affect which electrical carriers, i.e. electrons or holes, are used for operations of the semiconductor devices.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANGELICA ROSE E. GALVAN whose telephone number is (571)270-0122. The examiner can normally be reached Monday - Friday 8:30am - 6:00pm ET.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Joshua Benitez can be reached at (571) 270-1435. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/JAY C KIM/Primary Examiner, Art Unit 2815
/ANGELICA ROSE GALVAN/Examiner, Art Unit 2815
Prosecution Insights