Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claim 15 is rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention.
Claim 15 recites the limitations "first layer" and “second layer.” There is insufficient antecedent basis for this limitation in the claim. Claim 15 depends from Claim 13 and there is no introduction of a first or second layer it is unclear what structures are being referred to.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-5, 7, 9, 12-14 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Pat. Pub. No. 20120064689 to Hirota et al. (Hirota).
Regarding Claims 1-3, Hirota teaches in Figs. 13 and 15a-15i at least, semiconductor device, comprising:
a switching element (transistor, [0109]); and
a data storage structure (capacitor, [0138] and throughout) electrically connected to the switching element (definition of a DRAM, taught throughout), wherein the data storage structure includes,
a plurality of first electrodes 223;
a second electrode 225; and
a dielectric layer 224 disposed between the plurality of first electrodes and the second electrode,
wherein the second electrode includes a compound semiconductor layer doped with an impurity element (225c, B doped SiGe [0161], relevant to claims 2 and 3),
wherein the compound semiconductor layer includes two or more elements and includes a semiconductor material doped with the impurity element (225c, SiGe [0161]),
wherein the two or more elements include a first element and a second element (225c, SiGe [0161]),
wherein the first element is silicon (Si) (225c, SiGe [0161]),
but does not explicitly teach that a concentration of the impurity element in the compound semiconductor layer is in a range of about 0.1 at % to about 5 at %, and a concentration of the first element in the compound semiconductor layer is in a range of about 10 at % to about 15 at %. However, examiner takes official notice that dopant concentration in a semiconductor material directly affects its conductivity and SiGe stoichiometry directly affects its bandgap. Therefore, both are result effective variables that may be optimized by the person of ordinary skill to achieve application specific results (MPEP 2144.05(II)(B)). In this case and in Hirota, B doped SiGe is being used as a top electrode in the cap of a 1T1C DRAM, and Hirota is silent regarding the specifics of the material, motivating those of ordinary skill to optimize the material to best operate as an electrode for maximum conductivity and minimal bandgap.
Regarding Claim 4, Hirota teaches the semiconductor device of claim 1, wherein the second electrode further includes a conductive layer 225d on the compound semiconductor layer.
Regarding Claim 5, Hirota teaches the semiconductor device of claim 4, wherein the conductive layer includes a material (W, [0163]) that differs from a material of the compound semiconductor layer.
Regarding Claim 7, Hirota teaches the semiconductor device of claim 4, further comprising a contact structure 229 in contact with the second electrode.
Regarding Claim 9, Hirota teaches the semiconductor device of claim 7, wherein the contact structure is in contact with the conductive layer and spaced apart from the compound semiconductor layer (Fig. 13 shows a simplified view of the multilayer top electrode 225 of Figs. 15a-i; in the combination of Figs. 13 and 15 the contact structure 229 would contact the conductive layer 225d, spaced from b:SiGe layer 225c).
Regarding Claim 12, Hirota teaches the semiconductor device of claim 1, further comprising a bit line 216, wherein the switching element includes a gate electrode 211 and wherein the first electrodes are located at a level higher than that of the bit line and the gate electrode (see Fig. 13). It is not immediately clear Hirota teaches that extends in a direction that intersects the bit line, but even if Hirota cannot be interpreted such that the bit line does not intersect the word line, such an arrangement would not alter the mode of operation of either the invention or Hirota (MPEP 2144.04(VI)(C)).
Regarding Claim 13, Hirota teaches a semiconductor device, comprising:
a transistor that includes a first source/drain region 208 and a second source/drain region 209 that are spaced apart from each other, a channel region 206 interposed between the first and second source/drain regions, a gate dielectric layer 210 in contact with the channel region, and a gate electrode disposed on the gate dielectric layer;
a bit line 215 electrically connected to the first source/drain region; and
a data storage structure 223-225 that is electrically connected to the second source/drain region, wherein the data storage structure includes,
a first electrode 223 electrically connected to the second source/drain region;
a second electrode; and
a dielectric layer disposed between the first electrode and the second electrode,
wherein the second electrode includes a compound semiconductor layer doped with boron (B) and a conductive layer disposed on the compound semiconductor layer, wherein the compound semiconductor layer includes two or more elements, wherein the two or more elements include silicon (Si) and germanium (Ge), and wherein a concentration of the boron (B) in the compound semiconductor layer is within a range of about 0.1 at % to about 5 at %, and a concentration of the silicon (Si) in the compound semiconductor layer is within a range of about 10 at % to about 15 at % (see above rejection of Claim 1).
Regarding Claim 14, Hirota teaches the semiconductor device of claim 13, further comprising a contact structure in contact with the second electrode, wherein the contact structure is spaced apart from the compound semiconductor layer and contacts the conductive layer (see above rejection of Claim 9).
Regarding Claim 17, Hirota teaches the semiconductor device of claim 13, wherein the first and second source/drain regions are spaced apart from each other in a horizontal direction and are on the same level, and wherein the channel region is a horizontal channel region (see Fig. 13).
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Hirota as applied to claim 4 above, and further in view of U.S. Pat. Pub. No. 20180301457 to Lee et al. (Lee).
Regarding Claim 6, Hirota teaches the semiconductor device of claim 4, but does not explicitly teach that the conductive layer includes titanium (Ti). However, in analogous art, Lee teaches that W as taught by Hirota and Ti as claimed are obvious variants for top electrode materials in 1T1C DRAM devices [0084]. See MPEP 2144.06-07.
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Hirota as applied to claim 7 above, and further in view of U.S. Pat. Pub. No. 20030151083 to Matsui et al. (Matsui).
Regarding Claim 8, Hirota teaches the semiconductor device of claim 7, wherein the contact structure has a conductive layer but does not explicitly teach a barrier layer and a conductive layer on the barrier layer. However, in analogous art, Matsui teaches a contact structure 35 having a barrier layer and a conductive layer [0089]. It would have been obvious to the person of ordinary skill in the art before the time of filing to include the teaching of Matsui to prevent the migration of atoms from the conductive layer into the surrounding structures.
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Hirota as applied to claim 4 above, and further in view of U.S. Pat. Pub. No. 20020139973 to Nakuzato et al. (Nakuzato).
Regarding Claim 16, Hirota teaches the semiconductor device of claim 13, but does not explicitly teach that thefirst and second source/drain regions are vertically spaced apart from each other, and wherein the channel region is a vertical channel region. However, Nakuzato teaches in the abstract and throughout that vertical (as claimed) or lateral (as taught by Hirota) transistors may be used in 1T1C DRAM devices interchangeably. See MPEP 2144.06-07.
Allowable Subject Matter
Claims 10 and 11 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: the cited prior art does not show that the contact structure penetrates through the conductive layer and contacts or extends into the compound semiconductor layer.
Claims 18-20 are allowed.
Regarding Claim 18, Hirota a teaches semiconductor device, comprising:
first impurity regions 209 and second impurity regions 208/212 formed in the active regions 203 on both sides of the gate electrodes 211;
bit lines disposed 215 on the gate electrodes and electrically connected to the first impurity regions 209;
upper conductive patterns 221 disposed on side surfaces of the bit lines and electrically connected to the second impurity regions 208/212;
first electrodes 223
first electrodes 223 that vertically extend on the upper conductive patterns and are connected to the upper conductive patterns,
a dielectric layer 224 disposed on the first electrodes and the at least one supporter layer; and a second electrode disposed on the dielectric layer, wherein the second electrode includes
a compound semiconductor layer doped with an impurity element and a conductive layer disposed on the compound semiconductor layer,
wherein the compound semiconductor layer includes two or more elements and includes a semiconductor material doped with the impurity element,
wherein the two or more elements include a first element and a second element, and
wherein a concentration of the impurity element in the compound semiconductor layer is in a range of about 0.1 at % to about 5 at %, and a concentration of the first element in the compound semiconductor layer is in a range of about 10 at % to about 15 at % (See above rejection of Claim 1).
Hirota does not explicitly teach a device isolation layer that defines active regions on a substrate; and gate electrodes that cross the active regions and extend into the device isolation layer.
However, in analogous art, U.S. Pat. Pub. No. 20070138599 to Ahn at al. (Ahn) teaches in Fig. 7 at least, a gate electrode 67 that extends into device isolation layer 61 that defines active regions 55/56. It would have been obvious to the person of ordinary skill in the art before the time of filing to include the teaching of Ahn to increase integration in 1T1C DRAM devices, as taught by Ahn throughout starting at [0005].
Hirota and Ahn do not explicitly that the first electrodes are horizontally spaced apart from each other and at least one supporter layer disposed between horizontally adjacent first electrodes and in contact with the first electrodes.
Claims 19 and 20 are allowed as being dependent on Claim 18.
Conclusion
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/EVREN SEVEN/Primary Examiner, Art Unit 2812