DETAILED ACTION
This Office Action is in response to Applicant’s application 18/479,000 filed on September 30, 2023 in which claims 1 to 29 are pending.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The Information Disclosure Statement (IDS), filed on September 30, 2023 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosed therein has been considered by the Examiner.
Claim Objections
Claim 1 objected to because of the following informalities: Claim 1 recites ‘the substrate mount surface’ which lacks antecedent basis. Examiner suggests ‘the opposite substrate mount surface’. Appropriate correction is required.
Notation
References to patents will be in the form of [C:L] where C is the column number and L is the line number. References to pre-grant patent publications will be to the paragraph number in the form of [xxxx].
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-29 are rejected under 35 U.S.C. 103 as being unpatentable over U.S. 5,736,786 (Sankaran), U.S. 2017/0025336 (Padmanabhan) and U.S. 2022/0208661 (Zhang).
Regarding claim 1 and referring to annotated Figure 2, Sankaran discloses a method, comprising:
forming a thermal dissipation structure, 14 [3:4-8], comprising a thermally conductive insulator core, 20 [3:15-20], e.g., AlN, and having a device side surface, as annotated, and having an opposite substrate mount surface, as annotated;
mounting the substrate mount surface of the thermal dissipation structure to a device side surface of a substrate, 22 [2:63] as annotated and shown where
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24 is solder [2:61], the substrate having an opposite side surface, as shown;
placing die attach material, 16 [2:61] e.g., solder, on thermal conductors, 18 [3:26] e.g., copper, on the device side surface of the thermal dissipation structure, as annotated and shown;
mounting at least one semiconductor device die, 12 [3:1], on the device side surface of the thermal dissipation structure using the die attach material, as shown where solder 16 attaches die ,12, to DBC, 14;
forming electrical connections comprising wire bonds, 17 [2:62], or ribbon bonds on bond pads on the at least one semiconductor device die, as implied in Figure 2 where die will have bond pads to receive wire bonds.
Sankaran does not teach;
mounting the substrate mount surface of the thermal dissipation structure to a device side surface of a die pad of a package substrate, the die pad substrate having an opposite side surface forming a thermal pad;
forming electrical connections comprising wire bonds or ribbon bonds between leads on the package substrate spaced from the die pad and bond pads on the at least one semiconductor device die; and
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covering the electrical connections, the at least one semiconductor device die, and portions of the package substrate with mold compound, portions of the leads of the package substrate exposed from the mold compound and forming terminals for a semiconductor device package, and the thermal pad of the package substrate exposed from the mold compound and forming a thermal pad for the semiconductor device package.
Sankaran does not explicitly teach packaging the die in a QFN or QFP package for instance which entered mass production circa 1997.
Padmanabhan is directed to improvements and developments in packages for power semiconductor devices. Regarding claim 1 and referring to annotated Figures 6-9, Padmanabhan discloses a method, comprising: forming a thermal dissipation structure, e.g., 140 where at [0073] Padmanabhan teaches a DBC support may be bonded to die pad 132 as an alternative to insulating layer 140, comprising an insulator core as described at [0073], and having a device side surface and having an opposite substrate
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mount surface, as annotated; mounting the substrate mount surface of the thermal dissipation structure, 140/DBC, to a device side surface of a die pad, 132 [0073] as shown, of a package substrate, 130 [0073], the die pad substrate having an opposite side surface forming a thermal pad, 132 as shown; placing die attach material, 144 [0093] e.g., solder, on the device side surface of the thermal dissipation structure, 140/DBC, as annotated and shown; mounting at least one semiconductor device die, 10 [0070], on the device of the thermal dissipation structure, 140/DBC, using the die attach material, e.g. solder as shown; forming electrical connections comprising wire bonds, 127 [0078], or ribbon bonds between leads on the package substrate, 130 [0073] / 112 [0079], spaced from the die pad, 132, and bond pads, 16/18 [0079], on the at least one semiconductor device die, 10 [0063]; and covering the electrical connections, the at least one semiconductor device die, and portions of the package substrate with mold compound, as described at [0075] but not shown in the drawings, portions of the leads of the package substrate exposed from the mold compound and forming terminals for a semiconductor device package, i.e. a molded QFN package [0068]. Padmanabhan suggests 132 is a thermal pad which would be exposed by the EMC because EMC will expose the bottom of lead 110.
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Arguably, Padmanabhan does not explicitly teach the thermal pad of the package substrate exposed from the mold compound and forming a thermal pad for the semiconductor device package.
Zhang is directed to power electronics with QFN and QFP packaging. Referring to annotated Figure 1, Zhang teaches a QFN package [0016], and forming a thermal pad, 101 [0016], of the package substrate, 109 / 101 [0022] exposed from the mold compound, 120 [0019], and forming a thermal pad for the semiconductor device package as shown and described [0026].
At [0026], Zhang teaches;
[0026] The packaged electronic device 100 in this example provides a large and fully insulated top-side thermal pad for heat dissipation and easier thermal management during operation, with improved thermal performance compared with standard non-insulated QFN or QFP packages. The concepts of the disclosed examples can be used in other types and forms of packaged electronic devices. One example uses a 140 μm thick polymer layer 114, for example, a polymer-based, electrically isolated but thermally conductive material (e.g., thermal conductivity of 10 W per meter per degree K) to bond a thick copper plate 110 (e.g., 105 μm to 3 mm, such as 0.5 to 2 mm, for example 0.5 to 1 mm) and a standard copper lead frame for a QFN or QFP package. The exposed thermal pad area of this example increases more than 50% and the heat dissipation capability improves 40-60% depending on the copper plate thickness and thermal interface material used in a cooling system.
Zhang teaches the use of an exposed thermal pad for a QFN package increases the package heat dissipation capacity by 40-60 percent.
Taken as a whole, the prior art is directed to packaging for high power semiconductor devices. Sankaran teaches that DBC substrates are a good substrate technology for high power semiconductor packaging applications. Padmanabhan teaches that DBC substrates may be integrated in to conventional QFN packages and suggests the EMC will expose the die pad creating a thermal pad. Zhang explicitly teaches that QFN packages for semiconductor power devices configured with a thermal pad improves the heat dissipation capacity of the package, i.e. reduces the junction temperature of the device. An artisan would recognize that desirability of improving the reliability of the semiconductor device and package by improving the ability of the package to dissipate heat, i.e. failure in time events will decrease with a decrease in the junction temperature. An artisan would find it desirable to use a commercial HVM package for semiconductor assembly to enable system integrators to utilize industry standard package collateral to integrate the power semiconductor into a product while reducing packaging cost.
Accordingly it would have been obvious to a person of ordinary skill in the art at the time of Applicant’s invention to configure the method of claim 1 with mounting the substrate mount surface of the thermal dissipation structure to a device side surface of a die pad of a package substrate, the die pad substrate having an opposite side surface forming a thermal pad; forming electrical connections comprising wire bonds or ribbon bonds between leads on the package substrate spaced from the die pad and bond pads on the at least one semiconductor device die; and covering the electrical connections, the at least one semiconductor device die, and portions of the package substrate with mold compound, portions of the leads of the package substrate exposed from the mold compound and forming terminals for a semiconductor device package, and the thermal pad of the package substrate exposed from the mold compound and forming a thermal pad for the semiconductor device package, to implement a DBC substrate technology into a commercially available QFN/QFP package configuration with an improved thermal solution to reduce cost and increase reliability of the part and because the combination of familiar elements according to known methods is likely to be obvious when it does no more than yield predictable results. KSR International Co. v. Teleflex Inc., 550 U.S. 398, 416 (2007).
Regarding claim 2 which depends upon claim 1, Sankaran teaches forming a thermal dissipation structure comprising a thermally conductive insulator core, 20 [3:18-19], and having a device side surface and having an opposite substrate mount surface comprises forming thermal conductors, 18 [3:8], on a thermally conductive ceramic core, 20 [3:18-19], the thermal conductors on the device side surface, as shown, and on the substrate mount surface, as shown.
Regarding claim 3 which depends upon claim 2, Sankaran teaches the ceramic core of the thermal dissipation structure is of aluminum oxide, aluminum nitride, or silicon nitride at [3:18-19].
Regarding claim 4 which depends upon claim 3, Sankaran teaches the thermal conductors are of copper or copper alloy at [3:15].
Regarding claim 5 which depends upon claim 4, Sankaran teaches the thermal dissipation structure comprises a direct bonded copper (DBC) substrate at [3:4-5].
Regarding claim 6 which depends upon claim 2, Sankaran teaches the thermal dissipation structure further comprises a substrate mount material of solder 24 at [2:64], sintered silver, or die attach material (and) attaching the thermal dissipation structure to the die pad.
Regarding claim 7 which depends upon claim 1, Padmanabhan teaches at [0073] the package substrate is a metal lead frame consisting of copper, Alloy 42, stainless steel, or alloys thereof.
Regarding claim 8 which depends upon claim 1, Zhang teaches the thermal pad is exposed from a top side surface of the semiconductor device package, because the terminals are exposed at a board side surface of the semiconductor device package being the bottom of the package, and the semiconductor device package is a top side cooled quad flat no-lead (TsQFN) package, as discussed throughout.
Regarding claim 9 which depends upon claim 1, Zhang teaches the top side semiconductor package is useful for QFP and QFN at [0016]. Zhang teaches and suggests the thermal pad is exposed from a top side surface of the semiconductor device package, i.e., when leads are soldered to the board, the terminals are exposed at a board side surface of the semiconductor device package, i.e. the leads connect to the board, and the semiconductor device package is a leaded semiconductor device package with portions of the leads forming the terminals extending from the mold compound and having the thermal pad exposed from the mold compound, i.e., a QFP configuration assembled to a board.
Regarding claim 10 which depends upon claim 1, Examiner takes official notice that thermal pad is exposed from a board side surface of the semiconductor device package, the terminals are exposed from the board side surface of the semiconductor device package, and the semiconductor device package is a quad flat no-lead (QFN) package, is well known in the art and Applicant, c.f. Quek, Y.B., “QFN Layout Guidelines’, Texas Instruments July 2006 at page 1, figure 1.
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Accordingly, it would have been obvious to a person of ordinary skill in the art at the time of Applicant’s invention to configure the method of claim 1. Wherein thermal pad is exposed from a board side surface of the semiconductor device package, the terminals are exposed from the board side surface of the semiconductor device package, and the semiconductor device package is a quad flat no-lead (QFN) package to service customers using this configuration and because the combination of familiar elements according to known methods is likely to be obvious when it does no more than yield predictable results. KSR International Co. v. Teleflex Inc., 550 U.S. 398, 416
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(2007).
Regarding claim 11 which depends upon claim 10, at Figure 17 Padmanabhan teaches the package substrate is a metal lead frame, the die pad of the metal lead frame has a cavity extending into it from the device side surface of the lead frame, and the thermal dissipation structure,140/DBC, is mounted to the die pad in the cavity.
Accordingly it would have been obvious to a person of ordinary skill in the art at the time of Applicant’s invention to configure the method of claim 10 wherein the package substrate is a metal lead frame, the die pad of the metal lead frame has a cavity extending into it from the device side surface of the lead frame, and the thermal dissipation structure, is mounted to the die pad in the cavity because Padmanabhan teaches this is a suitable configuration to mount a DBC to a die pad and because the combination of familiar elements according to known methods is likely to be obvious when it does no more than yield predictable results. KSR International Co. v. Teleflex Inc., 550 U.S. 398, 416 (2007).
Regarding claim 12 which depends upon claim 11, an artisan would recognize the lead frame thickness as a results dependent factor effecting package reliability e.g. cracking and delamination, c.f. Abdullah S., et. al., “Thermal-mechanical Analysis of a Different Leadframe Thickness of Semiconductor Package under the Reflow Process.” American Journal of Applied Sciences, vol. 6, no. 4, 1 Apr. 2009, pp. 616–625, https://doi.org/10.3844/ajassp.2009.616.625. Padmanabhan and Zhang teach the lead frame thickness is greater than 0 mm.
Accordingly, it would have been obvious to a person of ordinary skill in the art at the time of Applicant’s invention to configure the method of claim 11 wherein the metal lead frame has a thickness of about 0.5 millimeters because in the case where the claimed ranges “overlap or lie inside ranges disclosed by the prior art”, a prima facie case of obviousness exists. In re Woodruff, 919 F.2d 1575 (Fed. Cir. 1990). See MPEP 2144.05.
Regarding claim 13 which depends upon claim 10, for the reasons discussed at claim 12 it would have been obvious to a person of ordinary skill in the art at the time of Applicant’s invention to configure the method of claim 10 wherein the package substrate is a metal lead frame, and the metal lead frame has a thickness of between 0.1 and 0.2 millimeters because in the case where the claimed ranges “overlap or lie inside ranges disclosed by the prior art”, a prima facie case of obviousness exists. In re Woodruff, 919 F.2d 1575 (Fed. Cir. 1990). See MPEP 2144.05.
Regarding claim 14 and referring to the discussion at claim 1, Sankaran discloses an apparatus, comprising: a thermal dissipation structure, 14 described as DBC at [3:4-24], mounted to the device side surface of a die substrate, 22 [2:63], the thermal dissipation structure comprising a thermally conductive insulator core, 20 e.g., AlN, and having thermal conductors, 18 [3:8], on a device side surface and on a substrate mount surface opposite the device side surface, as shown; at least one semiconductor device die, 12, [3:1], mounted to the device side surface of the thermal dissipation structure, as shown, using a die attach material, 16 e.g., solder [2:61]; electrical connections, 17 [2:62], on the bond pads on the at least one semiconductor device die, as implied at Figure 2.
Sankaran does not teach a package substrate having a die pad with a device side surface and a thermal pad on an opposite side surface of the die pad and having leads spaced from the die pad; a thermal dissipation structure mounted to the device side surface of the die pad, electrical connections formed between leads on the package substrate spaced from the die pad and bond pads on the at least one semiconductor device die; and mold compound covering the electrical connections, the at least one semiconductor device, and portions of the package substrate, portions of the leads of the package substrate exposed from the mold compound and forming terminals for a semiconductor device package, and the thermal pad of the package substrate exposed from the mold compound and forming a thermal pad for the semiconductor device package.
Padmanabhan teaches a package substrate, 130, having a die pad, 132, with a device side surface, as annotated, and suggests a thermal pad, e.g., 132 is a thermal pad, on an opposite side surface of the die pad, as shown, and having leads, 112/110, spaced from the die pad, 132; a thermal dissipation structure, 140/DBC, mounted to the device side surface of the die pad, as shown, the thermal dissipation structure comprising DBC; at least one semiconductor device die, 10, mounted to the device side surface of the thermal dissipation structure, as shown, using a die attach material, 144; electrical connections formed, 126, between leads, 110, on the package substrate spaced from the die pad, 132, and bond pads, 18, on the at least one semiconductor device die as shown; and suggests a mold compound covering the electrical connections, the at least one semiconductor device, and portions of the package substrate at [0075], i.e. a QFN package.
Arguably, Padmanabhan does not explicitly teach the thermal pad of the package substrate exposed from the mold compound and forming a thermal pad for the semiconductor device package.
Zhang teaches the thermal pad of the package substrate exposed from the mold compound and forming a thermal pad for the semiconductor device package.
Taken as a whole the prior art is directed to improvements in high power semiconductor packaging. Sankaran teaches that DBC substrates are a good technology for high power applications. Padmanabhan teaches that DBC substrates may be integrated in to conventional QFN packages. Zhang teaches that QFN packages for power devices configured with a thermal pad improve the heat dissipation capacity of the package. An artisan would recognize that desirability of improving the reliability of the semiconductor device and package by improving the ability of the package to dissipate heat, i.e. failure in time events will decrease with a decrease in operating temperature. An artisan would find it desirable to use a commercial package for semiconductor assembly to enable system integrators to utilize industry standards when the package in assembled onto a PCB with lower package cost.
Accordingly it would have been obvious to a person of ordinary skill in the art at the time of Applicant’s invention to configure the device of claim 14 with mounting the substrate mount surface of the thermal dissipation structure to a device side surface of a die pad of a package substrate, the die pad substrate having an opposite side surface forming a thermal pad; forming electrical connections comprising wire bonds or ribbon bonds between leads on the package substrate spaced from the die pad and bond pads on the at least one semiconductor device die; and covering the electrical connections, the at least one semiconductor device die, and portions of the package substrate with mold compound, portions of the leads of the package substrate exposed from the mold compound and forming terminals for a semiconductor device package, and the thermal pad of the package substrate exposed from the mold compound and forming a thermal pad for the semiconductor device package, to implement a DBC substrate technology into a commercially available QFN or QFP package configuration with an improved thermal solution to reduce cost and increase reliability and because the combination of familiar elements according to known methods is likely to be obvious when it does no more than yield predictable results. KSR International Co. v. Teleflex Inc., 550 U.S. 398, 416 (2007).
Regarding claim 15 which depends upon claim 14, Sankaran teaches the thermal dissipation structure comprises a thermally conductive ceramic core, 20 [3:19-19] e.g., AlN, having the thermal conductors, 18 [3:12], e.g., copper, on the device side surface and on the opposite substrate mount surface, as shown.
Regarding claim 16 which depends upon claim 15, Sankaran teaches the thermal dissipation structure comprises a direct bonded copper (DBC) substrate [3:4-5]. with copper conductors, 18 [3:12], on opposite sides of a ceramic core, as shown.
Regarding claim 17 which depends upon claim 16, Sankaran teaches the ceramic core comprises aluminum nitride, aluminum oxide, or silicon nitride at [3:19-20].
Regarding claim 18 which depends upon claim 14, Sankaran teaches the thermal dissipation structure comprises a direct bonded copper (DBC) substrate, at [3:4-5], and Padmanabhan teaches an DBC is also known as an insulated metal substrate (IMS), an active metal brazed substrate (AMS) or a laminate substrate.
Regarding claim 19 which depends upon claim 14, Zhang teaches and suggests at Figure 1 the thermal pad is exposed at a top side surface of the semiconductor device package (i.e. above the leads) and the at least one semiconductor device on the device side surface of the thermal dissipation structure faces a board side surface of the semiconductor device package, and the semiconductor device package forms a top side cooled, quad flat no-lead (TsQFN) package.
Regarding claim 20 which depends upon claim 14, Zhang teaches and suggests and Figure 1 the thermal pad is exposed at a top side surface of the semiconductor device package, i.e. lead are attached to the board, and the at least one semiconductor device on the device side surface of the thermal dissipation structure faces a board side surface of the semiconductor device package, and the semiconductor device package forms a leaded semiconductor device package with a thermal pad on the top side exposed from the mold compound, i.e. a QFP package configuration which is a suitable modification of the QFN package.
Regarding claim 21 which depends upon claim 14, Examiner takes official notice that a thermal pad is exposed at a board side of the semiconductor device package, and the at least one semiconductor device die on the device side surface of the thermal structure faces away from a board side surface of the semiconductor device package, and the semiconductor device package is a quad flat no-lead (QFN) package is well known as a configuration for a QFN power semiconductor package in the art.
Accordingly, it would have been obvious to a person of ordinary skill in the art at the time of Applicant’s invention to configure the method of claim 1. Wherein thermal pad is exposed from a board side surface of the semiconductor device package, the terminals are exposed from the board side surface of the semiconductor device package, and the semiconductor device package is a quad flat no-lead (QFN) package to service customers using this configuration and because the combination of familiar elements according to known methods is likely to be obvious when it does no more than yield predictable results. KSR International Co. v. Teleflex Inc., 550 U.S. 398, 416 (2007).
Regarding claim 22 which depends upon claim 14, Padmanabhan teaches the packaged semiconductor device is free from thermal interface material (TIM). Furthermore, Examiner takes the position that omission of an element is a species of obviousness when the function is not desired, e.g., package for a low power semiconductor device.
Regarding claim 23 which depends upon claim 14, Padmanabhan teaches at Figure 17 above the package substrate is a lead frame having a cavity extending from the device side surface into the die pad, and wherein the thermal dissipation structure is positioned in the cavity of the lead frame.
Accordingly it would have been obvious to a person of ordinary skill in the art at the time of Applicant’s invention to configure the device of claim 14 wherein the package substrate is a metal lead frame, the die pad of the metal lead frame has a cavity extending into it from the device side surface of the lead frame, and the thermal dissipation structure, is mounted to the die pad in the cavity because Padmanabhan teaches this is a suitable configuration to mount a DBC to a die pad and because the combination of familiar elements according to known methods is likely to be obvious when it does no more than yield predictable results. KSR International Co. v. Teleflex Inc., 550 U.S. 398, 416 (2007).
Regarding claim 24 which depends upon claim 14, Padmanabhan teaches the lead frame thickness is greater than about 0 mm and the package thickness is greater than 0 mm. Examiner takes official notice that QFN lead frames are known in the art to be about 0.5 mm thickness, c.f. U.S. 2014/0167238 at [0093]. Further the lead frame thickness is a known factor effecting package reliability e.g. cracking and delamination, as well as the package thickness, i.e. stiffness and boundary condition for the solder joint. Further package thickness is a factor effecting package reliability, i.e. stiffness and thermal mass effecting solder joint reliability.
Accordingly, it would have been obvious to a person of ordinary skill in the art at the time of Applicant’s invention to configure the device of claim 14 wherein the lead frame has a lead frame thickness measured at the die pad of about 0.5 millimeters, and the semiconductor device package has a thickness of between 1.0-2.0 millimeters because in the case where the claimed ranges “overlap or lie inside ranges disclosed by the prior art”, a prima facie case of obviousness exists. In re Woodruff, 919 F.2d 1575 (Fed. Cir. 1990). See MPEP 2144.05.
Regarding claim 25 and referring to the discussion above Sankaran discloses semiconductor device package, comprising: a die substrate, 22; a thermal dissipation structure, 14, mounted to the device side surface of the die substrate, the thermal dissipation structure comprising a thermally conductive insulator core, 20 AlN, and thermal conductors, 18 copper, on a substrate mount surface of the thermally conductive insulator core and on a device side surface of the thermally conductive insulator core arranged for mounting at least one semiconductor device, as shown; at least one semiconductor device die, 12. mounted to the device side surface of the thermal dissipation structure using a die attach material, 16; electrical connections, 17, formed on bond pads on the at least one semiconductor device die.
Sankaran does not teach a metal lead frame having a die pad with a device side surface and having a thermal pad on an opposite side surface of the die pad, and having leads spaced from the die pad; a thermal dissipation structure mounted to the device side surface of the die pad, electrical connections formed between leads on the lead frame and bond pads on the at least one semiconductor device die; and mold compound covering the electrical connections, the at least one semiconductor device, and portions of the package substrate, portions of the leads of the package substrate exposed from the mold compound and forming terminals for a semiconductor device package, and the thermal pad of the package substrate exposed from the mold compound and forming a thermal pad for the semiconductor device package
Padmanabhan teaches a metal lead frame, 130 copper, having a die pad, 132 [0073], with a device side surface, as shown, and having a thermal pad on an opposite side surface of the die pad, as annotated and shown, and having leads, 110/112, spaced from the die pad, as shown; a thermal dissipation structure, 140/DBC, mounted to the device side surface of the die pad, 132 as shown, electrical connections, 126, formed between leads on the lead frame and bond pads on the at least one semiconductor device die, 10 as shown; and mold compound covering the electrical connections, the at least one semiconductor device, and portions of the package substrate, portions of the leads of the package substrate exposed from the mold compound and forming terminals for a semiconductor device package, at [0075] where this structure corresponds to a QFN or QFP package, and suggests the thermal pad of the package substrate exposed from the mold compound and forming a thermal pad for the semiconductor device package.
Arguable Padmanabhan does not explicitly teach the thermal pad of the package substrate exposed from the mold compound and forming a thermal pad for the semiconductor device package.
Zhang teaches for a QFN / QFP package the thermal pad of the package substrate exposed from the mold compound and forming a thermal pad for the semiconductor device package.
For the reasons discussed at claim 1 it would have been obvious to a person of ordinary skill in the art at the time of Applicant’s invention to configure the device of claim 20 comprising a metal lead frame having a die pad with a device side surface and having a thermal pad on an opposite side surface of the die pad, and having leads spaced from the die pad; a thermal dissipation structure mounted to the device side surface of the die pad, electrical connections formed between leads on the lead frame and bond pads on the at least one semiconductor device die; and mold compound covering the electrical connections, the at least one semiconductor device, and portions of the package substrate, portions of the leads of the package substrate exposed from the mold compound and forming terminals for a semiconductor device package, and the thermal pad of the package substrate exposed from the mold compound and forming a thermal pad for the semiconductor device package to implement a DBC substrate technology into a commercially available package configuration with an improved thermal solution to reduce cost and increase reliability of the part and because the combination of familiar elements according to known methods is likely to be obvious when it does no more than yield predictable results. KSR International Co. v. Teleflex Inc., 550 U.S. 398, 416 (2007).
Regarding claim 26 which depends upon claim 25, Sankaran teaches the thermal dissipation structure comprises a direct bonded copper (DBC) substrate as noted above.
Regarding claim 27 which depends upon claim 25, Sankaran teaches the thermal dissipation structure comprises the thermally conductive insulator core that is aluminum oxide, aluminum nitride, or silicon nitride, as noted above.
Regarding claim 28 which depends upon claim 25, Zhang teaches the thermal pad is exposed on a top side surface of the semiconductor device package facing away from a board side surface of the semiconductor device package, and the at least one semiconductor device is mounted on the thermal dissipation structure on the die pad and facing the board side surface, forming a top side cooled quad flat no-lead (TsQFN) package, as noted above.
Regarding claim 29 which depends upon claim 25, Examiner takes official notice that a thermal pad exposed on a board side surface of the semiconductor device package, and the at least one semiconductor device is mounted on the thermal dissipation structure on the die pad and facing away from the board side surface, the semiconductor device package forming a quad flat no-lead (QFN) package is a well-known in the power semiconductor QFN art and accordingly it would have been obvious to a person of ordinary skill in the art at the time of Applicant’s invention to configure the device of claim 25 as such to service integrators using this configuration and because the combination of familiar elements according to known methods is likely to be obvious when it does no more than yield predictable results. KSR International Co. v. Teleflex Inc., 550 U.S. 398, 416 (2007).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure is listed on the notice of references cited.
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/J.E. Schoenholtz/Primary Examiner, Art Unit 2893