DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 7-12 and 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Nakamura et al. (US 2006/0284283 A1) in view of Lin et al. (US 2018/0130789 A1)
Regarding Claim 1, Nakamura (Fig. 16-24) discloses a method of forming an integrated circuit, comprising:
in a first implant ( p-type impurity 161a to 161c), forming in a semiconductor substrate (150) a first (166a) and second (166c) region of a first semiconductor type (p-type), each of the first (166a) and second (166c) region having a first dopant concentration [0082-0053];
in a second implant ( p-type impurity 163a to 163c), forming in the semiconductor substrate (150) a third (167a) and fourth region (167c) of the first semiconductor type (p-type), the third region (167a) at least partially overlapping the first region (166a) and the fourth region (167c) at least partially overlapping the second region (166c), each of the third and fourth region having a second dopant concentration different than the first dopant concentration (“p-type impurity ion 163a to 163c is carried out at concentration higher than the ion implantation of the p-type impurity 161a to 161c.”) [0084];
forming one of a diode anode (an anode electrode wiring 169h) or a diode cathode in the second and fourth regions (166c, 167c).
Nakamura does not explicitly disclose forming a transistor source within the first and third regions
Lin (Fig. 10) a transistor source (114, 118) within a first and third regions (See regions inside 110)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify a method of forming an integrated circuit in Nakamura in view of Lin such that a transistor source within the first and third regions in order to have laterally spaced regions: one for the source-down transistor and one for the ESD diode. [0014-0018]
Regarding Claim 7, Nakamura (Fig. 16-24) in view of Lin discloses the method of claim 1,
forming, in addition to forming the diode anode or the diode cathode in the second and fourth regions (166c 167c), the other of the diode anode or the diode cathode (“A cathode electrode wiring 105g electrically connected with the n-type impurity layer 103c”) in the semiconductor substrate (150), and wherein
a reverse bias breakdown voltage, between the diode anode (105g) and the diode cathode (105g), is responsive to an intersection depth between the first dopant concentration and the second dopant concentration. (see depth difference between 106c and 104c).
The Examiner notes that as long there is intersection depth between the first dopant concentration and the second dopant concentration, the limitation a reverse bias breakdown voltage, between the diode anode and the diode cathode, is responsive to an intersection depth between the first dopant concentration and the second dopant concentration is considered to be met since value for reverse bias breakdown voltage is not established.
Regarding Claim 9, Nakamura (Fig. 16-24) in view of Lin discloses the method of claim 1 and further comprising:
forming a transistor drain (166b) and transistor channel (area under 156b, 157b) in the semiconductor substrate (150) and a transistor gate (157b) in a fixed position relative to the semiconductor substrate (150); and
forming, in addition to forming one of the diode anode or the diode cathode in the second and fourth regions (166c 167c), forming the other of the diode anode or the diode cathode (“A cathode electrode wiring 105g electrically connected with the n-type impurity layer 103c”) in the semiconductor substrate (150),
Regarding Claim 10, Nakamura (Fig. 16-24) in view of Lin discloses the method of claim 9: wherein:
a transistor threshold voltage, relative to the transistor source and the transistor gate (165a and 157b), is responsive to the second dopant concentration (dopant concentration in p-type impurity ion 163a to 163c); and
a reverse bias breakdown voltage, between the diode anode and the diode cathode (159h and 169g), is responsive to an intersection point between the first dopant concentration (dopant concentration in the first (166a) and second (166c) region having a first dopant concentration [0082-0053]); and the second dopant concentration. (“dopant concentration in p-type impurity ion 163a to 163c is carried out at concentration higher than the ion implantation of the p-type impurity 161a to 161c.”) [0084]);
The Examiner notes that as long there is intersection depth between the first dopant concentration and the second dopant concentration, the limitation a reverse bias breakdown voltage, between the diode anode and the diode cathode, is responsive to an intersection depth between the first dopant concentration and the second dopant concentration is considered to be met since value for reverse bias breakdown voltage is not established.
Regarding Claim 11, Nakamura (Fig. 16-24) discloses the method of claim 1, wherein
the first semiconductor type includes boron. (“ B is ion implanted into the source region and the drain region” )
Regarding Claim 12, Nakamura (Fig. 16-24) discloses the method of claim 11, wherein the transistor source is formed from an n-type semiconductor. (“the n-channel field effect transistor, a source electrode wiring 169a electrically connected with the n-type impurity layer 165a is formed on the n-type impurity layer 165a in the source region”).
Regarding Claim 14, Nakamura (Fig. 16-24) discloses the method of claim 1, wherein
the forming one of the diode anode or the diode cathode forms at least a portion of the diode anode. (Fig. 22-24)
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2 is/are rejected under 35 U.S.C. 103 as being unpatentable over Nakamura et al. (US 2006/0284283 A1) in view of Lin et al. (US 2018/0130789 A1) and further in view of Hu et al. (US 2004/0106236 A1) and Suzuki et al. (US 2006/0255411 A1).
Regarding Claim 2, Nakamura (Fig. 16-24) in view of Lin discloses the method of claim 1, wherein
Nakamura n view of Lindoes not explicitly disclose a third implant is performed to form the transistor source and form one of the diode anode or the diode cathode.
Hu (Fig. 1) discloses a third implant step comprises the forming a transistor source [0008] (“During this implantation process n-type dopant species are also implanted into the source region 85 to further increase the n-doping concentration” [0010]
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method in Nakamura n view of Lin and Hu such that a third implant step comprises the forming a transistor source in order to further increase the n-doping concentration and have double diffused source region [0008-0010].
Nakamura in view of Lin and Hu does not explicitly disclose a third implant step comprises the forming one of a diode anode or a diode cathode
Suzuki (Fig. 1B, 4A) discloses a third implant step comprises the forming one of a diode anode or a diode cathode (3A) [0038-0041].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method in Nakamura in view of Lin and Hu and Suzuki such that a third implant step comprises the forming a transistor source in order to reduce a parasitic resistance in the N type region and contacts an electrode of the cathode [0038].
Claim(s) 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Nakamura et al. (US 2006/0284283 A1) in view of Lin et al. (US 2018/0130789 A1) and further in view of Suzuki et al. (US 2006/0255411 A1).
Regarding Claim 15, Nakamura (Fig. 16-24) in view of Lin discloses the method of claim 11,
Nakamura in view of Lin does not explicitly disclose further comprising forming a coupling from the transistor source to the diode anode.
Suzuki (Fig. 1B) discloses forming a coupling from a transistor source (S) to the diode anode (A).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method in Nakamura in view of Lin and Suzuki further comprising forming a coupling from the transistor source to the diode anode in order to have diode protect transistor from an electrostatic discharge [0037].
Allowable Subject Matter
Claims 3-6, 16 and 21 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claims 17-19 and 22 is allowable.
The following is an examiner's statement of reasons for allowance:
With regards to claim 17, none of the prior art teaches or suggests, alone or in combination, “concurrently implanting a third dopant of an opposite second conductivity type in a fifth region overlapping the first and third regions and in a sixth region overlapping the second and fourth regions, the fifth region implementing a transistor source and the sixth region implementing a first terminal of a diode;…implanting a third fourth dopant of the first conductivity type in a seventh region spaced apart from the sixth region and extending into the semiconductor substrate and implementing a second terminal of the diode; forming a transistor gate over the semiconductor substrate adjacent the transistor source; and electrically connecting the transistor source to the second diode terminal of the diode and the transistor gate to the first diode terminal of the diode.” in the combination required by the claim.
Claims 18-19 are allowed by virtue of their dependency on the independent claim 17.
With regards to claim 22, none of the prior art teaches or suggests, alone or in combination, “forming a transistor source within the first and third regions; and forming one of a diode anode or a diode cathode in the second and fourth regions; and wherein: the transistor source extends a first depth from a surface of the semiconductor substrate into the semiconductor substrate; and the first region extends a second depth from the surface of the semiconductor substrate into the semiconductor substrate, the second depth being no greater than fifty percent of the first depth.” in the combination required by the claim.
Response to Arguments
`Applicant’s arguments, see pages 8-9, filed 06/29/2026, with respect to the rejection(s) of claim(s) 1 under 35 U.S.C. 102(A1) as being anticipated by Nakamura et al. (US 2006/0284283 A1) have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made under 35 U.S.C. 103 as being unpatentable over Nakamura et al. (US 2006/0284283 A1) in view of Lin et al. (US 2018/0130789 A1)
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DMITRIY YEMELYANOV whose telephone number is (571)270-7920. The examiner can normally be reached M-F 9a.m.-6p.m.
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/DMITRIY YEMELYANOV/Examiner, Art Unit 2891
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