Prosecution Insights
Last updated: May 29, 2026
Application No. 18/479,006

INTEGRATED CIRCUIT DEVICE WITH FERROELECTRIC CAPACITOR

Non-Final OA §102§103
Filed
Sep 30, 2023
Priority
Apr 17, 2023 — provisional 63/459,802
Examiner
AHMAD, KHAJA
Art Unit
2813
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Texas Instruments Incorporated
OA Round
1 (Non-Final)
81%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 81% — above average
81%
Career Allowance Rate
755 granted / 933 resolved
+12.9% vs TC avg
Strong +27% interview lift
Without
With
+26.6%
Interview Lift
resolved cases with interview
Typical timeline
2y 4m
Avg Prosecution
30 currently pending
Career history
976
Total Applications
across all art units

Statute-Specific Performance

§101
0.5%
-39.5% vs TC avg
§103
86.0%
+46.0% vs TC avg
§102
10.8%
-29.2% vs TC avg
§112
0.9%
-39.1% vs TC avg
Black line = Tech Center average estimate • Based on career data from 933 resolved cases

Office Action

§102 §103
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . DETAILED ACTION This office action is in response to the Applicant Election filled on 02/11/2026. Currently, claims 1-20 are pending in the application. Claims 16-20 have been withdrawn from consideration. Election/Restrictions Applicant's election without traverse of Group I, claims 1-15, in the reply filed on 02/11/2026 is acknowledged, there being no allowable generic or linking claim. Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention. (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claims 1-3, 5-6 and 11-15 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kim et al (US 20010007366 A1). Regarding claim 1, Figures 5-7 of Kim disclose a method of forming an integrated circuit, comprising: forming a first conductive (112, [0028]) member affixed relative to a semiconductor substrate (100, [0028]); forming a second conductive member (120, [0029]) affixed relative to the semiconductor substrate (100); and forming a ferroelectric member (D, 114/116/118, [0030]-[0031]) between the first and second conductive members, the ferroelectric member having a first portion (114) including a first atomic ratio of lead (Pb) relative to other materials in the first portion and a second portion (116) including a second atomic ratio of lead relative to other materials in the second portion, the second atomic ratio differing from the first atomic ratio (claim 6 of Kim, 114 having higher Pb than the layer 116) ([0031]). Regarding claim 2, Figures 5-7 of Kim disclose that the method of claim 1 wherein the first portion (114) provides a first layer of material ([0031]). Regarding claim 3, Figures 5-7 of Kim disclose that the method of claim 2 wherein the second portion (116) provides a second layer of material ([0031]). Regarding claim 5, Figures 5-7 of Kim disclose that the method of claim 3 wherein the first atomic ratio is greater than the second atomic ratio ([0031]), and wherein the first layer (114) has a thickness less than a thickness of the second layer (116)(seed layer 114 is anticipated to be lower in thickness than the main ferroelectric layer 116). Regarding claim 6, Figures 5-7 of Kim disclose that the method of claim 3 wherein the ferroelectric member (114/116/118, [0031]) includes lead, zirconium, and titanium, and wherein each of the first and second lead atomic ratio is a ratio of lead relative to at least zirconium and titanium ([0031]). Regarding claim 11, Figures 5-7 of Kim disclose that the method of claim 1 wherein the first portion (114) and the second portion (116) provide a lead gradient between the first and second conductive members ([0031], Pb is higher in 114 than in 116). Regarding claim 12, Figures 5-7 of Kim disclose that the method of claim 1 wherein the ferroelectric member (114/116/118) includes lead, zirconium, and titanium ([0031]). Regarding claim 13, Figures 5-7 of Kim disclose that the method of claim 1 and further comprising: forming a transistor (at 104, [0028]) relative to the semiconductor substrate (100), the transistor having at least a first source/drain region (106/107) in a portion of the semiconductor substrate (100); and forming a conductive path (110, [0028]) from the first source/drain region (106) to one of the first conductive member (112) or the second conductive member. Regarding claim 14, Figures 5-7 of Kim disclose that the method of claim 1 and further comprising: forming the first conductive member (112) affixed at a first distance relative to the semiconductor substrate (100); forming the second conductive member (120) affixed at a second distance, greater than the first distance, relative to the semiconductor substrate (100); and forming the ferroelectric member (D) having a greater lead concentration (in 114) closer to the first conductive member (112) as compared to closer to the second conductive member (120). Regarding claim 15, Figures 5-7 of Kim disclose that the method of claim 1 and further comprising forming a plurality of cells relative to the semiconductor substrate (100), wherein the step of forming a first conductive member (112) includes forming a first conductive member for each cell in the plurality of cells, wherein the step of forming a second conductive member (120) includes forming a second conductive member for each cell in the plurality of cells, and wherein the step of forming a ferroelectric member (114/116/118, D) includes forming a ferroelectric member for each cell in the plurality of cells (Figure 7 is a sectional view of a FRAM device which is anticipated to have many cells as claimed). Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 4 and 7 are rejected under 35 U.S.C. 103 as being obvious over Kim et al (US 20010007366 A1). Regarding claims 4 and 7, Figures 5-7 of Kim do not explicitly teach that the method of claim 3 wherein the first atomic ratio is greater than the second atomic ratio, and wherein the first layer has a thickness from 5 nm to 30 nm. Or The method of claim 6 wherein the first atomic ratio is in a range from 1.06 to 1.08 and wherein the second atomic ratio is in a range from 1.04 to 1.06. However, it would have been obvious to one having ordinary skill in the art at the time of the invention was made to use the above claimed ranges in order to form an improved ferroelectric device with lower cost since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working range involves only routine skill in the art. In re Aller, 105 USPQ 233. Claims 8-10 are rejected under 35 U.S.C. 103 as being obvious over Kim et al (US 20010007366 A1) in view of WANG (US 20080157155 A1). Regarding claims 8-10, Figures 5-7 of Kim do not teach that the method of claim 3 wherein the step of forming a ferroelectric member forms the first layer of material at a first flow rate and forms the second layer of material at a second flow rate different than the first flow rate; and The method of claim 8 wherein a faster of the first flow rate and the second flow rate is at least 1.5 ml/min. Or The method of claim 8 wherein a faster of the first flow rate and the second flow rate is from 1.5 ml/min to 2.5 ml/min. However, WANG is a pertinent art which teaches a semiconductor device (FeRAM) having a ferroelectric capacitor, wherein WANG teaches a ferroelectric film 127 made of PZT is formed using a flow rate such as 0.32 ml per minute, 0.2 ml per minute, and 0.2 ml per minute for forming a PZT layer having lead ratio 0.45 ([0060]). Thus, it would have been obvious to one having ordinary skill in the art at the time of the invention was made to use the above claimed ranges in order to form an improved ferroelectric device with desired ratio of lead (Pb) in the ferroelectric layer with lower cost since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working range involves only routine skill in the art. In re Aller, 105 USPQ 233. Examiner Notes A reference to specific paragraphs, columns, pages, or figures in a cited prior art reference is not limited to preferred embodiments or any specific examples. It is well settled that a prior art reference, in its entirety, must be considered for all that it expressly teaches and fairly suggests to one having ordinary skill in the art. Stated differently, a prior art disclosure reading on a limitation of Applicant's claim cannot be ignored on the ground that other embodiments disclosed were instead cited. Therefore, the Examiner's citation to a specific portion of a single prior art reference is not intended to exclusively dictate, but rather, to demonstrate an exemplary disclosure commensurate with the specific limitations being addressed. In re Heck, 699 F.2d 1331, 1332-33,216 USPQ 1038, 1039 (Fed. Cir. 1983) (quoting In re Lemelson, 397 F.2d 1006, 1009, 158 USPQ 275, 277 (CCPA 1968)). In re: Upsher-Smith Labs. v. Pamlab, LLC, 412 F.3d 1319, 1323, 75 USPQ2d 1213, 1215 (Fed. Cir. 2005); In re Fritch, 972 F.2d 1260, 1264, 23 USPQ2d 1780, 1782 (Fed. Cir. 1992); Merck& Co. v. BiocraftLabs., Inc., 874 F.2d 804, 807, 10 USPQ2d 1843, 1846 (Fed. Cir. 1989); In re Fracalossi, 681 F.2d 792,794 n.1, 215 USPQ 569, 570 n.1 (CCPA 1982); In re Lamberti, 545 F.2d 747, 750, 192 USPQ 278, 280 (CCPA 1976); In re Bozek, 416 F.2d 1385, 1390, 163 USPQ 545, 549 (CCPA 1969). Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to KHAJA AHMAD whose telephone number is (571)270-7991. The examiner can normally be reached on Monday-Friday, 8:00 AM - 5:00 PM (Eastern Time). If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, GAUTHIER STEVEN B, can be reached on (571)270-0373. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice . Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /KHAJA AHMAD/Primary Examiner, Art Unit 2813
Read full office action

Prosecution Timeline

Sep 30, 2023
Application Filed
Apr 27, 2026
Non-Final Rejection mailed — §102, §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
81%
Grant Probability
99%
With Interview (+26.6%)
2y 4m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 933 resolved cases by this examiner. Grant probability derived from career allowance rate.

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