Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 10/2/2023, 4/24/2024, and 5/2/2025 is acknowledged. The submission is in compliance with the provisions of 37 CFR 1.97.
Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1 – 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Banerjee (US 20210249996 A1).
Regarding Independent Claim 1, XXX teaches,
A differential power amplifier circuit (Fig. 1, 100), comprising:
a first differential power amplifier (Fig. 1, 112A and 152A) including first and second cross-coupled neutralization capacitors (Fig. 1, 108A and 108B); and
a second differential power amplifier (Fig. 1, 112B and 152B), coupled in parallel with the first differential power amplifier (Fig. 1, 112A and 152A), including a plurality of multi-gate transistors (Fig. 1, 112C and 152C).
Regarding claim 2,
The differential power amplifier circuit (Fig. 1, 100) according to claim 1, wherein the multi-gate transistors comprise dual-gate transistors (Fig. 1, the transistors function as dual-gate transistors. See paragraph [0008], “… a transistor stack comprising at least two stacked transistor units for amplifying the input signals, which transistor stack is arranged between the input and the output; wherein each of the at least two stacked transistor units comprises a plurality of controllable segments, each controllable segment comprising a segment transistor, wherein source terminals of the segment transistors of each of the controllable segments within each stacked transistor unit are connected together, drain terminals of the segment transistors of each of the controllable segments within each stacked transistor unit are connected together and gate terminals of the segment transistors of each of the controllable segments within each stacked transistor unit are connected together, wherein each segment transistor further comprises a back gate terminal for setting a body bias of the segment transistor, wherein at least two of the segment transistors within each of the at least two stacked transistor units have independently connected back gate terminals for independently controlling the body bias of the at least two of the segment transistors…”).
Regarding claim 3,
The differential power amplifier circuit (Fig. 1, 100) according to claim 1, wherein the first differential power amplifier (Fig. 1, 112A and 152A) includes:
an input stage (Fig. 1, input stage of 112A and 152A);
an output stage (Fig. 1, output stage of 112A and 152A); and
first and second parallel branches (Fig. 1, 112A and 152A, respectively) connected between the input stage and the output stage, wherein each of the first and second parallel branches includes a drive transistor and a power transistor (Fig. 1, both elements 112A and 152A comprise an N number of transistors that can function as drive and power transistors) connected in series between the input stage and the output stage (Fig. 1, input and output stages of 112A and 152A), wherein a gate of the drive transistor is connected to the input stage (Fig. 1, the gate of the transistors in 112A and 152A are connected to the input stage) and wherein the gate of the power transistor is connected to a bias voltage (See paragraph [0008], “… wherein each segment transistor further comprises a back gate terminal for setting a body bias of the segment transistor, wherein at least two of the segment transistors within each of the at least two stacked transistor units have independently connected back gate terminals for independently controlling the body bias of the at least two of the segment transistors; and a control unit, which is configured to control the body bias of the plurality of controllable segments of each of the at least two stacked transistor units, wherein the control unit is configured to control the body bias for selecting an amplifier class of each of the controllable segments of each of the at least two stacked transistor units”).
Regarding claim 4,
The differential power amplifier circuit (Fig. 1, 100) according to claim 3, wherein the first cross-coupled neutralization capacitor is coupled between the gate of the drive transistor in the first parallel branch and a node between the drive transistor and the power transistor in the second parallel branch (Fig. 1, 108A is connected between the gate of a transistor in 112A and to a node between two transistors in 152A), and wherein the second cross-coupled neutralization capacitor is coupled between the gate of the drive transistor in the second parallel branch and a node between the drive transistor and the power transistor in the first parallel branch (Fig. 1, 108B is connected between the gate of a transistor in 152A and to a node between two transistors in 112A).
Regarding claim 5,
The differential power amplifier circuit (Fig. 1, 100) according to claim 3, wherein the input stage includes:
an input node (Fig. 1, input node at 102); and
an input transformer (Fig. 1, 102) including two magnetically coupled input windings, wherein one of the input windings is connected between the input node and any of ground and another input node, and wherein another of the input windings is connected at opposite ends to the gates of the drive transistors in the first and second parallel branches, respectively (Fig. 1, 102 is connected between the input and 106, and is respectively connected to the gates of the transistors in both 112A and 152A).
Regarding claim 6,
The differential power amplifier circuit (Fig. 1, 100) according to claim 3, wherein the second differential power amplifier includes (Fig. 1, 112B and 152B):
first and second parallel branches (Fig. 1, 112B and 152B, respectively), wherein each of the first and second branches of the second differential power amplifier includes a multi-gate transistor (Fig. 1, respectively, 112B and 152B are connected to 112C and 152C), wherein a first gate of the multi-gate transistor is connected to the input stage of the first differential power transistor, and wherein a second gate of the multi-gate transistor is connected to the bias voltage (Fig. 1, the transistors in 112C and 152C are respectively connected to the input stage and to a voltage bias).
Regarding claim 7,
The differential power amplifier circuit (Fig. 1, 100) according to claim 6, wherein the multi-gate transistor in the first parallel branch of the second differential power amplifier is connected between ground and a node between the power transistor in the first parallel branch of the first differential power amplifier and the output stage (Fig. 1, 112C is connected between a ground and the output stage), and wherein the multi-gate transistor in the second parallel branch of the second differential power amplifier is connected between ground and a node between the power transistor in the second parallel branch of the first differential power amplifier and the output stage (Fig. 1, 152C is connected between a ground and the output stage).
Regarding claim 8,
The differential power amplifier circuit (Fig. 1, 100) according to claim 6, wherein the differential power amplifier circuit is implemented using a plurality of X power cells (Fig. 1, each of the transistors in 112A, 112B, 112C, 152A, 152B, and 152C are implemented using N number of transistors).
Regarding claim 9,
The differential power amplifier circuit (Fig. 1, 100) according to claim 8, wherein each drive transistor and each power transistor in the first differential power amplifier is implemented using 1 power cell (Fig. 1, the first transistor in 112A, 112B, 112C, 152A, 152B, and 152C function as a single drive transistor), and wherein each dual-gate transistor in the second differential power amplifier is implemented using (X-4)/4 merged power cells (Fig. 1, each of the transistors in 112A, 112B, 112C, 152A, 152B, and 152C are implemented using N number of transistors).
Regarding claim 10,
The differential power amplifier circuit (Fig. 1, 100) according to claim 8, wherein each drive transistor in the first differential power amplifier is implemented using 1 power cell (Fig. 1, the first transistor in 112A, 112B, 112C, 152A, 152B, and 152C function as a single drive transistor), each power transistor in the first differential power amplifier is implemented using 3 power cells (Fig. 1, 112A, 112B, 112C, 152A, 152B, and 152C comprise N number of transistors. Therefore, the next 3 transistors after the first transistor that functions as the drive transistor in 112A, 112B, 112C, 152A, 152B, and 152C function as the power transistors, respectively), and wherein each dual-gate transistor in the second differential power amplifier is implemented using (X-8)/4 merged power cells (Fig. 1, each of the transistors in 112A, 112B, 112C, 152A, 152B, and 152C are implemented using N number of transistors).
Regarding claim 11,
A differential power amplifier circuit (Fig. 1, 100), comprising:
a first differential power amplifier (Fig. 1, 112A and 152A) including first and second parallel branches (Fig. 1, 112A and 152A, respectively), wherein the first differential power amplifier includes first and second neutralization capacitors (Fig. 1, 108A and 108B) cross-coupled between the first and second parallel branches (Fig. 1, 112A and 152A, respectively); and
a second, multi-gate differential power amplifier (Fig. 1, 112B and 152B) including first and second parallel branches (Fig. 1, 112B and 152B, respectively), wherein the first and second parallel branches of the second differential power amplifier are coupled to the first and second parallel branches, respectively, of the first differential power amplifier (Fig. 1, 112B and 152B are coupled to 11A and 152A, respectively).
Regarding claim 12,
The differential power amplifier circuit (Fig. 1, 100) according to claim 11, wherein the first differential power amplifier (Fig. 1, 112A and 152A) includes:
an input stage (Fig. 1, input stage of 112A and 152A);
an output stage (Fig. 1, output stage of 112A and 152A); and
first and second parallel branches (Fig. 1, 112A and 152A, respectively) connected between the input stage and the output stage, wherein each of the first and second parallel branches includes a drive transistor and a power transistor (Fig. 1, both elements 112A and 152A comprise an N number of transistors that can function as drive and power transistors) connected in series between the input stage and the output stage (Fig. 1, input and output stages of 112A and 152A), wherein a gate of the drive transistor is connected to the input stage (Fig. 1, the gate of the transistors in 112A and 152A are connected to the input stage) and wherein the gate of the power transistor is connected to a bias voltage (See paragraph [0008], “… wherein each segment transistor further comprises a back gate terminal for setting a body bias of the segment transistor, wherein at least two of the segment transistors within each of the at least two stacked transistor units have independently connected back gate terminals for independently controlling the body bias of the at least two of the segment transistors; and a control unit, which is configured to control the body bias of the plurality of controllable segments of each of the at least two stacked transistor units, wherein the control unit is configured to control the body bias for selecting an amplifier class of each of the controllable segments of each of the at least two stacked transistor units”).
Regarding claim 13,
The differential power amplifier circuit (Fig. 1, 100) according to claim 11, wherein the first cross-coupled neutralization capacitor is coupled between the gate of the drive transistor in the first parallel branch and a node between the drive transistor and the power transistor in the second parallel branch (Fig. 1, 108A is connected between the gate of a transistor in 112A and to a node between two transistors in 152A), and wherein the second cross-coupled neutralization capacitor is coupled between the gate of the drive transistor in the second parallel branch and a node between the drive transistor and the power transistor in the first parallel branch (Fig. 1, 108B is connected between the gate of a transistor in 152A and to a node between two transistors in 112A).
Regarding claim 14,
The differential power amplifier circuit (Fig. 1, 100) according to claim 11, wherein the input stage includes:
an input node (Fig. 1, input node at 102); and
an input transformer (Fig. 1, 102) including two magnetically coupled input windings, wherein one of the input windings is connected between the input node and any of ground and another input node, and wherein another of the input windings is connected at opposite ends to the gates of the drive transistors in the first and second parallel branches, respectively (Fig. 1, 102 is connected between the input and 106, and is respectively connected to the gates of the transistors in both 112A and 152A).
Regarding claim 15,
The differential power amplifier circuit (Fig. 1, 100) according to claim 11, wherein each of the first and second parallel branches of the second, multi-gate differential power amplifier includes a multi-gate transistor (Fig. 1, 112C and 152C function as dual-gate transistors. See paragraph [0008], “… a transistor stack comprising at least two stacked transistor units for amplifying the input signals, which transistor stack is arranged between the input and the output; wherein each of the at least two stacked transistor units comprises a plurality of controllable segments, each controllable segment comprising a segment transistor, wherein source terminals of the segment transistors of each of the controllable segments within each stacked transistor unit are connected together, drain terminals of the segment transistors of each of the controllable segments within each stacked transistor unit are connected together and gate terminals of the segment transistors of each of the controllable segments within each stacked transistor unit are connected together, wherein each segment transistor further comprises a back gate terminal for setting a body bias of the segment transistor, wherein at least two of the segment transistors within each of the at least two stacked transistor units have independently connected back gate terminals for independently controlling the body bias of the at least two of the segment transistors…”), wherein a first gate of the multi-gate transistor is connected to the input stage of the first differential power transistor, and wherein a second gate of the multi-gate transistor is connected to the bias voltage (Fig. 1, the transistors in 112C and 152C are respectively connected to the input stage and to a voltage bias).
Regarding claim 16,
The differential power amplifier circuit (Fig. 1, 100) according to claim 15, wherein the multi-gate transistor in the first parallel branch of the second differential power amplifier is connected between ground and a node between the power transistor in the first parallel branch of the first differential power amplifier and the output stage (Fig. 1, 112C is connected between a ground and the output stage), and wherein the multi-gate transistor in the second parallel branch of the second differential power amplifier is connected between ground and a node between the power transistor in the second parallel branch of the first differential power amplifier and the output stage (Fig. 1, 152C is connected between a ground and the output stage).
Regarding claim 17,
The differential power amplifier circuit (Fig. 1, 100) according to claim 15, wherein the differential power amplifier circuit is implemented using a plurality of X power cells (Fig. 1, each of the transistors in 112A, 112B, 112C, 152A, 152B, and 152C are implemented using N number of transistors).
Regarding claim 18,
The differential power amplifier circuit (Fig. 1, 100) according to claim 17, wherein each drive transistor and each power transistor in the first differential power amplifier is implemented using 1 power cell (Fig. 1, the first transistor in 112A, 112B, 112C, 152A, 152B, and 152C function as a single drive transistor), and wherein each dual-gate transistor in the second differential power amplifier is implemented using (X-4)/4 merged power cells (Fig. 1, each of the transistors in 112A, 112B, 112C, 152A, 152B, and 152C are implemented using N number of transistors).
Regarding claim 19,
The differential power amplifier circuit (Fig. 1, 100) according to claim 15, wherein each drive transistor in the first differential power amplifier is implemented using 1 power cell (Fig. 1, the first transistor in 112A, 112B, 112C, 152A, 152B, and 152C function as a single drive transistor), each power transistor in the first differential power amplifier is implemented using 3 power cells (Fig. 1, 112A, 112B, 112C, 152A, 152B, and 152C comprise N number of transistors. Therefore, the next 3 transistors after the first transistor that functions as the drive transistor in 112A, 112B, 112C, 152A, 152B, and 152C function as the power transistors, respectively), and wherein each dual-gate transistor in the second differential power amplifier is implemented using (X-8)/4 merged power cells (Fig. 1, each of the transistors in 112A, 112B, 112C, 152A, 152B, and 152C are implemented using N number of transistors).
Regarding claim 20,
A radio frequency (RF) differential power amplifier circuit (Fig. 1, 100), comprising:
an RF input stage for receiving an RF input signal (Fig. 1, input stage by 102, 112A and 152A);
a first differential power amplifier (Fig. 1, 112A and 152A) including first and second parallel branches coupled to the RF input stage (Fig. 1, 112A and 152A, respectively), wherein the first differential power amplifier includes first and second neutralization capacitors (Fig. 1, 108A and 108B) cross-coupled between the first and second parallel branches;
a second, multi-gate differential power amplifier (Fig. 1, 112B and 152B) including first and second parallel branches (Fig. 1, 112B and 152B, respectively) coupled to the RF input stage, wherein the first and second parallel branches of the second differential power amplifier are coupled to the first and second parallel branches, respectively, of the first differential power amplifier (Fig. 1, 112B and 152B are coupled to 11A and 152A, respectively); and
an RF output stage (Fig. 1, output stage by 104) coupled to the first and second differential power amplifiers for outputting an amplified RF signal (Fig. 1, 112A, 112B, 152A, and 152B are respectively coupled to the output stage by 104).
Conclusion
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/JOSE E PINERO/Examiner, Art Unit 2843
/ANDREA LINDGREN BALTZELL/Supervisory Patent Examiner, Art Unit 2843