Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Currently, claims 1-10 are pending and examined below.
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d). Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement (IDS)
The information disclosure statement submitted on 10/02/2023 ("10-02-23 IDS") is in compliance with the provisions of 37 CFR 1.97. Accordingly, the 10-02-23 IDS is being considered by the examiner.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: SEMICONDUCTOR DEVICE HAVING CHIP CAPACITOR CONNECTED TO SEMICONDUCTOR CHIP WITH WIRES
Claim Rejections - 35 USC § 1021
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 7 and 9 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Pub. No. US 2023/0089615 A1 to Agawa et al. ("Agawa").
Figs. 24 and 25 as well as Fig. 9 of Agawa have been provided to support the rejection below:
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Regarding independent claim 1, Agawa teaches a semiconductor device (see Figs. 24 and 25 as well as Fig. 9, for example) comprising:
a base material 32 having a first terminal 31a (para [0087] - “Each of the pads 21, 22, 23, and 24 is connected to any one or more of the leads 31 (31a, 31b, and 31c), the base 32, and the Si capacitor chip 1.”);
a semiconductor chip 2A having a first electrode pad 21 electrically connected with the first terminal 31a (see Fig. 25), a second electrode pad 24 to which a power supply potential VDD is to be supplied (from 31; see also FIG. 9), and a third electrode pad 22Aa to which a reference potential VGND is to be supplied (see Figs. 9 and 25), and mounted on the base material 32 via a first member 55 (para [0192] - “A conductive layer 55”);
a chip capacitor 1 having a first electrode 16A and a second electrode 16B, and mounted on the semiconductor chip 2A via a second member 7 (para [0283]- “conductive sheet 7”);
a first wire 51 or 51a electrically connecting the first electrode pad 21 with the first terminal 31 or 31a (see Fig. 24);
a second wire 74 (para [0294] - “an interconnect 72”; Fig. 25 shows the longer interconnect 74 adjacent to the interconnect 72.) electrically connecting the second electrode pad 24 with the first electrode 16A without going through the base material 32 (see Fig. 24);
a third wire 72 (para [0294] - “an interconnect 72”) electrically connecting the third electrode pad 22Aa with the second electrode 16B without going through the base material 32; and
a resin sealing body 39 (para [0048] - “The package member (also referred to as a sealing member) 39 is, for example, an insulating resin (for example, a molding resin).”) sealing the semiconductor chip 2A, the chip capacitor 1, the first wire 51, the second wire 74 and the third wire 72,
wherein a length of each of the second wire 74 and the third wire 72 is shorter than a length of the first wire 51 or 51a (see Fig. 25).
Regarding claim 7, Agawa teaches wherein, in plan view, a plurality of electrode pads including the first electrode pad 21, a second electrode pad 24 and a third electrode pad 22Aa arranged along each side of the semiconductor chip 2A and arranged in plural rows, and
wherein each of the second electrode pad 24 and the third electrode pad 22Aa is arranged in a first row, the first row is a row located at the most inner side of the semiconductor chip 2A among the plural rows in plan view.
Regarding claim 9, Agawa teaches the second member 7 is a die attach film (para [0293]- “The conductive sheet 7 extends between the two chips 1 and 2A in the X direction.”).
Allowable Subject Matter
The following is a statement of reasons for the indication of allowable subject matter:
Claim 2 is objected to for depending on a rejected base claim 1, but would be allowable if it is rewritten in independent form to include all of the limitations of the base claim 1 or the base claim 1 is amended to include all of the limitations of claim 2.
Claims 3-6 and 8 are allowable for depending on the allowable claim 2.
Claim 10 is objected to for depending on a rejected base claim 1, but would be allowable if it is rewritten in independent form to include all of the limitations of the base claim 1 or the base claim 1 is amended to include all of the limitations of claim 10.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Pub. No. US 2023/0005897 A1 to Kanda et al.
Pub. No. US 2022/0302076 A1 to Iida
Pub. No. US 2021/0327831 A1 to Ha et al.
Pub. No. US 2020/0168530 A1 to Male et al.
Pub. No. US 2019/0312005 A1 to Pon et al.
Pub. No. US 2017/0162490 A1 to Katsumura et al.
Pub. No. US 2014/0252551 A1 to Dix et al.
Pub. No. US 2012/0068306 A1 to Song et al.
Pub. No. US 2010/0123215 A1 to Pan et al.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHAEL JUNG whose telephone number is (408) 918-7554. The examiner can normally be reached on 8:30 A.M. to 7 P.M.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eliseo Ramos-Feliciano can be reached on (571) 272-7925. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/MICHAEL JUNG/Primary Examiner, Art Unit 2817 02 December 2025
1 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status