Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Detailed Action
This office action is in response to applicant’s communication filed on 10/02/23. Claims 1-27 are pending in this application.
Claim Rejections Under 35 U.S.C. §102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1- are rejected under 35 U.S.C. §102 as being unpatentable over Sills (US 20200111908 A1).
Regarding claim 1, Sills discloses semiconductor device comprising: a substrate 102; a lower electrode 104 on the substrate; a first buffer layer (106, 114, 214, 314 A’s)on the lower electrode, the first buffer layer including first indium (see para [0029]); an oxide semiconductor layer on the first buffer layer(106, 114, 214, 314 B’s), the oxide semiconductor layer including second indium (see para [0029]); a gate insulating layer 314 on the oxide semiconductor layer (314b); a gate electrode 324 on the gate insulating layer 314; and an upper electrode 316 on the oxide semiconductor layer, wherein a content of the first indium in the first buffer layer is greater than a content of the second indium in the oxide semiconductor layer (see para [0030]), wherein the first buffer layer(106, 114, 214, 314 A’s) is between the lower electrode104 and the oxide semiconductor layer(106, 114, 214, 314 B’s), and wherein the upper electrode and the lower electrode are spaced apart from each other in a perpendicular direction extending perpendicular to the substrate(see figs 1-3).
Regarding claim 2, Sills discloses the semiconductor device of claim 1, wherein the first buffer layer is in contact with each of the lower electrode and the oxide semiconductor layer (see figs 1-3, where (106, 114, 214, 314 A’s) contact 314b and 314).
Regarding claim 3, Sills discloses the semiconductor device of claim 1, wherein the first buffer layer comprises at least one of InGaZnO, InGaO, InSnO, InZnO, and InO (see paras [0029] and [0030]).
Regarding claim 4, Sills disclose the semiconductor device of claim 1, wherein the lower electrode includes Zn having a content of 10 at% or less(see para [0029] and [0030] disclosing non-zn materials).
Regarding claim 5, Sills disclose the semiconductor device of claim 1, wherein Zn content in the first buffer layer is less than the In content in the first buffer layer(see paras [0029] and [0030]).
Regarding claim 6, Sills disclose the semiconductor device of claim 1, wherein the first buffer layer has a thickness in a range from about 1 Ǻ to about 50 Ǻ (see para [0044]).
Regarding claim 7, Sills disclose the semiconductor device of claim 1, wherein the oxide semiconductor layer comprises an oxide comprising at least one of Zn, Sn, Ga, and Hf (see para [0032] disclosing zn and sn and Ga and hf).
Regarding claim 8, Sills discloses the semiconductor device of claim 1, wherein the content of the second indium in the oxide semiconductor layer is greater in an area relatively close to the first buffer layer than in an area relatively far from the first buffer layer (see paras [0029] and [0030]).
Regarding claim 9, Sills discloses the semiconductor device of claim 1, further comprising a metal oxide layer between the lower electrode and the first buffer layer, wherein the metal oxide layer comprises a same metal as a metal included in the lower electrode (see 116 between 114 and 114bca).
Regarding claim 10, Sills disclose the semiconductor device of claim 1, wherein the oxide semiconductor layer comprises InGaZnO, ZrInZnO, InGaZnO4, ZnInO, In2O3, HfInZnO, or any combination thereof(see para [0032] disclosing zn and sn and Ga and hf).
Regarding claim 11, Sills discloses the semiconductor device of claim 1, wherein the oxide semiconductor layer comprises the second indium and zinc (Zn), and a content of the second indium in the oxide semiconductor layer is greater than or equal to a content of Zn in the oxide semiconductor layer(see paras [0029] and [0030]).
Regarding claim 12, Sills disclose the semiconductor device of claim 1, wherein the lower electrode comprises at least one of tungsten (W), cobalt (Co), nickel (Ni), iron (Fe), titanium (Ti), molybdenum (Mo), chromium (Cr), zirconium (Zr), hafnium (Hf), niobium (Nb), tantalum (Ta), silver (Ag), gold (Au), aluminum (Al), copper (Cu), tin (Sn), vanadium (V), ruthenium (Ru), platinum (Pt), zinc (Zn), or magnesium (Mg) (see para [0040]).
Regarding claim 13, Sills disclose the semiconductor device of claim 1, wherein the gate electrode surrounds a circumference of the oxide semiconductor layer (see figs 1-2 disclosing 124 surrounds).
Regarding claim 14, Sills disclose the semiconductor device of claim 1, further comprising a second buffer layer between the oxide semiconductor layer and the upper electrode (see 114c).
Regarding claim 15, Sills disclose the semiconductor device of claim 1, wherein the first buffer layer is in contact with a side surface of the lower electrode, and at least a portion of the oxide semiconductor layer is offset from the lower electrode and the upper electrode in a horizontal direction that extends parallel with the substrate, and the portion of the oxide semiconductor layer extends in the perpendicular direction between at least a position that overlaps the lower electrode in the horizontal direction and another position that overlaps the upper electrode in the horizontal direction (see figs 1-3).
Regarding claim 16, Sills disclose the semiconductor device of claim 1, wherein the oxide semiconductor layer, the gate insulating layer, and the gate electrode are arranged such that the oxide semiconductor layer, the gate insulating layer, and the gate electrode have respective length directions that are parallel with each other and parallel to the perpendicular direction, and the oxide semiconductor layer, the gate insulating layer, and the gate electrode are arranged in a horizontal direction extending parallel with the substrate such that the oxide semiconductor layer, the gate insulating layer, and the gate electrode at least partially overlap with each other in the horizontal direction (see figs 1-3 disclosing flat layers formed as a stack).
Regarding claim 17, Sills disclose the semiconductor device of claim 1, wherein the oxide semiconductor layer has a U-shaped cross-section (see figs 1e disclosing 114/120 is u shaped).
Regarding claim 18, Sills disclose the semiconductor device of claim 1, wherein the oxide semiconductor layer comprises a first oxide semiconductor layer that has an L-shape having a length dimension and a width dimension extending perpendicular to each other such that the length dimension of the first oxide semiconductor layer extends in the perpendicular direction, and a second oxide semiconductor layer that is symmetrically arranged with respect to the first oxide semiconductor layer with respect to the perpendicular direction such that the first and second oxide semiconductor layers have reflection symmetry around a first axis of symmetry that extends in the perpendicular direction, and the gate electrode comprises a first gate electrode having a length dimension that extends in the perpendicular direction, and a second gate electrode that is symmetrically arranged with respect to the first gate electrode with respect to the perpendicular direction such that the first and second gate electrodes have reflection symmetry around a second axis of symmetry that extends in the perpendicular direction (see fig 2, where 214 has an L shape and is arranged in symmetry and gate layers are horizontal).
Regarding claim 19, Sills disclose the semiconductor device of claim 1, wherein the lower electrode, the first buffer layer, and the oxide semiconductor layer have a same width as each other (see fig 1c, disclosing same widths).
Regarding claim 20, Sills discloses a method of manufacturing a semiconductor device, the method comprising: arranging a lower electrode 104 on a substrate 102; depositing, on the lower electrode, a buffer layer including first indium (106, 114, 214, 314 A’s, see para [0029] disclosing indium); depositing, on the buffer layer, an oxide semiconductor layer including second indium(106, 114, 214, 314 B’s); depositing a gate insulating layer 314 on the oxide semiconductor layer 314b; depositing a gate electrode 324 on the gate insulating layer314; and depositing an upper electrode 316on the oxide semiconductor layer(106, 114, 214, 314 A’s), wherein a content of the first indium in the buffer layer is greater than a content of the second indium in the oxide semiconductor layer (see para [0030]), wherein the buffer layer is between the lower electrode and the oxide semiconductor layer (see figs 1-3), and wherein the upper electrode and the lower electrode are spaced apart from each other in a perpendicular direction that extends perpendicular to the substrate (see figs 1-3).
Regarding claim 21, Sills disclose the method of claim 20, wherein the buffer layer is in contact with each of the lower electrode and the oxide semiconductor layer (see fig 1c).
Regarding claim 22, Sills disclose the method of claim 20, wherein the buffer layer comprises at least one of InGaZnO, InGaO, InSnO, InZnO, and InO (see paras [0029] and [0030]).
Regarding claim 23, Sills disclose the method of claim 20, wherein the buffer layer has a thickness in a range from about 1 Ǻ to about 50 Ǻ(see para [0044]).
Regarding claim 24, Sills disclose the method of claim 20, wherein the depositing of the buffer layer on the lower electrode comprises an atomic layer deposition (ALD) process (see para [0036]).
Regarding claim 25, Sills disclose the method of claim 20, wherein the depositing of the oxide semiconductor layer comprises an atomic layer deposition (ALD) process(see para [0036]).
Regarding claim 26, Sills disclose the method of claim 20, wherein the lower electrode comprises Zn having a content of 10 at% or less (see para [0029] and [0030] disclosing non-zn materials).
Regarding claim 27, Sills disclose the method of claim 20, wherein Zn content in the buffer layer is less than the In content in the buffer layer(see paras [0029] and [0030]).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to EDWARD CHIN whose telephone number is (571)270-1827. The examiner can normally be reached M-F 9AM-5PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Britt Hanley can be reached at (571) 270-3042. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/EDWARD CHIN/Primary Examiner, Art Unit 2893