Prosecution Insights
Last updated: April 19, 2026
Application No. 18/479,432

THREE-DIMENSIONAL MEMORY DEVICE CONTAINING PHOSPHORUS-DOPED SILICON OXIDE ION-GETTERING STRUCTURES AND METHODS OF FORMING THE SAME

Non-Final OA §102
Filed
Oct 02, 2023
Examiner
JUNG, MICHAEL YOO LIM
Art Unit
2817
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Western Digital Technologies Inc.
OA Round
1 (Non-Final)
82%
Grant Probability
Favorable
1-2
OA Rounds
2y 5m
To Grant
93%
With Interview

Examiner Intelligence

Grants 82% — above average
82%
Career Allow Rate
1019 granted / 1241 resolved
+14.1% vs TC avg
Moderate +11% lift
Without
With
+11.2%
Interview Lift
resolved cases with interview
Typical timeline
2y 5m
Avg Prosecution
41 currently pending
Career history
1282
Total Applications
across all art units

Statute-Specific Performance

§101
2.1%
-37.9% vs TC avg
§103
29.0%
-11.0% vs TC avg
§102
35.0%
-5.0% vs TC avg
§112
27.6%
-12.4% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1241 resolved cases

Office Action

§102
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . DETAILED ACTION Currently, claims 1-20 are pending and examined below. Information Disclosure Statement (IDS) Two information disclosure statements submitted on 10/02/2023 ("10-02-23 IDS") and 10/03/2024 (“10-03-24 IDS”) are in compliance with the provisions of 37 CFR 1.97. Accordingly, the 10-02-23 IDS and 10-03-24 IDS are being considered by the examiner. Claim Rejections - 35 USC § 1021 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 1, 2, 5 and 15 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Pub. No. US 2020/0251488 A1 to Iwai et al. ("Iwai"). Fig. 40A of Iwai has been annotated to support the rejection below: [AltContent: arrow] PNG media_image1.png 351 435 media_image1.png Greyscale [AltContent: textbox (LIT)] Regarding independent claim 1, Iwai teaches a three-dimensional memory device (see Fig. 40A as annotated above), comprising: a pair of alternating stack of insulating layers 32 (para [0183] - “Each sacrificial material layer 42 may be replaced with an electrically conductive layer 46.”; para [0182] - “a pair of insulating layers 32”; para [0192] - “the alternating stack (32, 46)”) and electrically conductive layers 46, wherein the pair of alternating stacks 32, 46 are laterally spaced from each other by a lateral isolation trench 19 (para [0318] - “support opening 19”); memory openings 49 (para [0133] - “memory openings 49”) vertically extending through a respective alternating stack of the pair of alternating stacks 32, 46; memory opening fill structures 58 (para [0280] - “Each memory opening fill structure 58 including a first memory stack structure 55A is herein referred to as a first memory opening fill structure 58A.”) located in a respective one of the memory openings 49 and comprising a respective vertical semiconductor channel 60 (para [0282] - “Each vertical semiconductor channel 60”) and a respective vertical stack of memory elements 50 (para [0287] - “a respective second memory film 50”); and a lateral isolation trench fill structure LIT located in the lateral isolation trench 19, wherein phosphorus-doped silicon oxide portions 65 (para [0132] - “If silicon oxide is used for the retro-stepped dielectric material portion 65, the silicon oxide of the retro-stepped dielectric material portion 65 may...be doped with dopants such as B, P, and/or F.”) are located on sidewalls of the lateral isolation trench 19 at levels of the insulating layers 32. Regarding claim 2, Iwai teaches the vertical semiconductor channel 60 that comprises p-type silicon (para [0284] - “In case the first conductivity type is p-type, the dopants of the first conductivity type may include boron atoms.”); and a n-type silicon source region doped with phosphorus atoms (para [0191] - “…a source region 61 having a doping of a second conductivity type may be formed within the semiconductor material layer 10”; para [0289] - “a doping of the second conductivity type that is the opposite of the first conductivity type”; para [0284] discloses that when the dopant type is n-type, phosphor atoms can be used.) that is located below the lateral isolation trench fill structure LIT. Regarding claim 5, Iwai teaches the phosphorus-doped silicon oxide portions 65 that are located on the sidewalls of the lateral isolation trench 19. Regarding independent claim 15, Iwai teaches a method of forming a three-dimensional memory device (see Fig. 40A as annotated above), comprising: forming two alternating stacks a pair of insulating layers 32 (para [0183] - “Each sacrificial material layer 42 may be replaced with an electrically conductive layer 46.”; para [0182] - “a pair of insulating layers 32”; para [0192] - “the alternating stack (32, 46)”) and electrically conductive layers 46, wherein the two alternating stacks 32, 46 are laterally spaced from each other by a lateral isolation trench 19 (para [0318] - “support opening 19”); forming memory openings 49 (para [0133] - “memory openings 49”) each of the two alternating stacks 32, 46; forming memory opening fill structures 58 (para [0280] - “Each memory opening fill structure 58 including a first memory stack structure 55A is herein referred to as a first memory opening fill structure 58A.”) comprising a respective vertical semiconductor channel 60 (para [0282] - “Each vertical semiconductor channel 60”) and a respective vertical stack of memory elements 50 (para [0287] - “a respective second memory film 50”) in the respective memory openings 49; forming phosphorus-doped silicon oxide portions 65 (para [0132] - “If silicon oxide is used for the retro-stepped dielectric material portion 65, the silicon oxide of the retro-stepped dielectric material portion 65 may...be doped with dopants such as B, P, and/or F.”) are located on sidewalls of the lateral isolation trench 19 at levels of the insulating layers 32; and forming a lateral isolation trench fill structure LIT located in the lateral isolation trench 19. Allowable Subject Matter The following is a statement of reasons for the indication of allowable subject matter: Claim 3 is objected to for depending on a rejected base claim 1 and the intervening claim 2, but would be allowable if it is rewritten in independent form to include all of the limitations of the base claim 1 and the intervening claim 2 or the base claim 1 is amended to include all of the limitations of claim 3 and the intervening claim 2. Claim 4 is allowable for depending on the allowable claim 3. Claim 6 is objected to for depending on a rejected base claim 1 and the intervening claim 5, but would be allowable if it is rewritten in independent form to include all of the limitations of the base claim 1 and the intervening claim 5 or the base claim 1 is amended to include all of the limitations of claim 6 and the intervening claim 5. Claim 7 is allowable for depending on the allowable claim 6. Claim 8 is objected to for depending on a rejected base claim 1 and the intervening claim 5, but would be allowable if it is rewritten in independent form to include all of the limitations of the base claim 1 and the intervening claim 5 or the base claim 1 is amended to include all of the limitations of claim 8 and the intervening claim 5. Claims 9 and 10 are allowable for depending on the allowable claim 8. Claim 11 is objected to for depending on a rejected base claim 1, but would be allowable if it is rewritten in independent form to include all of the limitations of the base claim 1 or the base claim 1 is amended to include all of the limitations of claim 11. Claim 12 is objected to for depending on a rejected base claim 1, but would be allowable if it is rewritten in independent form to include all of the limitations of the base claim 1 or the base claim 1 is amended to include all of the limitations of claim 12. Claim 13 is allowable for depending on the allowable claim 12. Claim 14 is objected to for depending on a rejected base claim 1, but would be allowable if it is rewritten in independent form to include all of the limitations of the base claim 1 or the base claim 1 is amended to include all of the limitations of claim 14. Claim 16 is objected to for depending on a rejected base claim 15, but would be allowable if it is rewritten in independent form to include all of the limitations of the base claim 15 or the base claim 15 is amended to include all of the limitations of claim 16. Claims 17 and 18 are allowable for depending on the allowable claim 16. Claim 19 is objected to for depending on a rejected base claim 15, but would be allowable if it is rewritten in independent form to include all of the limitations of the base claim 15 or the base claim 15 is amended to include all of the limitations of claim 19. Claim 20 is objected to for depending on a rejected base claim 15, but would be allowable if it is rewritten in independent form to include all of the limitations of the base claim 15 or the base claim 15 is amended to include all of the limitations of claim 20. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure: Pub. No. US 2024/0349500 A1 to Zhou et al. Pub. No. US 2024/0260266 A1 to Hosoda et al. Pub. No. US 2020/0395408 A1 to Takahashi et al. Pub. No. US 2016/0358933 A1 to Rabkin et al. Pub. No. US 2016/0218059 A1 to Nakada et al. Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHAEL JUNG whose telephone number is (408) 918-7554. The examiner can normally be reached on 8:30 A.M. to 7 P.M. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eliseo Ramos-Feliciano can be reached on (571) 272-7925. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /MICHAEL JUNG/Primary Examiner, Art Unit 2817 29 November 2025 1 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status
Read full office action

Prosecution Timeline

Oct 02, 2023
Application Filed
Nov 29, 2025
Non-Final Rejection — §102 (current)

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Prosecution Projections

1-2
Expected OA Rounds
82%
Grant Probability
93%
With Interview (+11.2%)
2y 5m
Median Time to Grant
Low
PTA Risk
Based on 1241 resolved cases by this examiner. Grant probability derived from career allow rate.

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