DETAILED ACTION
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
General Remarks
2. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection.
3. When responding to this office action, applicants are advised to provide the examiner with paragraph numbers in the application and/or references cited to assist the examiner in locating appropriate paragraphs.
4. Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable
interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
Claim Rejections - 35 USC § 102
5. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
6. Claims 1-3, 5 and 7-15 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Miyake, Daisuke et al. (Pub No. US 20210265379 A1) (hereinafter, Miyake).
Re Claim 1, Miyake teaches a semiconductor structure, comprising:
an alternating stack (Alternating stack; 132/246; Figs 9B/24; ¶[0161]) of insulating layers (Insulating layers; 132; Fig 24; ¶[0070]) and electrically conductive layers (Electrically conductive/sacrificial layers; 142/242/246; Figs 9B/24; ¶[0161]);
Miyake, Fig 9B: Forming memory openings in alternating stack and source layers
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a memory opening (Memory opening; 49; Fig 9B; ¶[0106]) vertically extending through the alternating stack;
a memory opening fill structure (Blocking dielectric/Charge storage/Tunneling dielectric; 52/54/56; Semiconductor channel material layer; 60/60L; Source region; 61; Dielectric core; 62; Drain region; 63; Fig 15E; ¶¶[0112 - 0115, 0122, 0124]) located in the memory opening and comprising a memory film (Blocking dielectric/Charge storage/Tunneling dielectric; 52/54/56; Fig 15E; ¶[0114]), a vertical semiconductor channel (Semiconductor channel material layer; 60/60L; Fig 15E; ¶[0115]), and a semiconductor source cap structure (Source region; 61; Fig 15E; ¶[0147]) which is at least partially laterally surrounded by the memory film and which contacts the vertical semiconductor channel; and
a source layer (Upper and/or lower source-level semiconductor layer; 116/112; Fig 15E; ¶[0060]) contacting at least a first end surface segment (Bottom segment; 61B; Fig 15E; ¶[0153]) of the semiconductor source cap structure.
Miyake, Fig 15E: 3D memory device with memory fill structures and source layers
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Re Claim 2, Miyake teaches the semiconductor structure of Claim 1, further comprising a source-side spacer layer (Source contact layer; 114; Fig 15E; ¶[0143]) located between the source layer (Upper and/or lower source-level semiconductor layer; 116/112; Fig 15E; ¶[0060]) and the alternating stack (Alternating stack; 132/246; Figs 9B/24; ¶[0161]), wherein:
the memory opening (Memory opening; 49; Fig 9B; ¶[0106]) also vertically extends through (49 extends through 116; Fig 9B) the source-side spacer layer; and
the semiconductor source cap structure (Source region; 61; Fig 15E; ¶[0147]) is laterally surrounded by the source-side spacer layer.
Re Claim 3, Miyake teaches the semiconductor structure of Claim 2, wherein:
the semiconductor source cap structure (Source region; 61; Fig 15E; ¶[0147]) further comprises an annular conical surface segment (Convex annular surface/Tubular segment; 61S/61T; Fig 15E; ¶[0152]) adjoined to the first end surface segment (Bottom segment; 61B; Fig 15E; ¶[0153]); and
the annular conical surface segment is laterally surrounded by the memory film (Blocking dielectric/Charge storage/Tunneling dielectric; 52/54/56; Fig 15E; ¶[0114]) and by the source-side spacer layer (Source contact layer; 114; Fig 15E; ¶[0143]).
Re Claim 5, Miyake teaches the semiconductor structure of Claim 3, wherein the semiconductor source cap structure (Source region; 61; Fig 15E; ¶[0147]) further comprises a second end surface segment (Convex annular surface/Tubular segment; 61S/61T; Fig 15E; ¶[0152]) that contacts a convex end surface (Convex surface of 60 in contact with 61S; Fig 15E) of the vertical semiconductor channel (Semiconductor channel material layer; 60/60L; Fig 15E; ¶[0115]).
Re Claim 7, Miyake teaches the semiconductor structure of Claim 3, wherein:
the source-side spacer layer (Source contact layer; 114; Fig 15E; ¶[0143]) comprises an opening (Opening surrounding 50/53/61T/61L/61B/61P; Fig 15E) having a tapered conical sidewall (Surfaces of 61T/61L/61B/61P are tapered and conical (annular); Fig 15E; ¶[0153]); and
the tapered conical sidewall comprises a first tapered conical surface segment (Segment from 61L upwards towards edge of 53; Fig 15E) that contacts a conical surface segment (Sidewalls of 116; i.e. in shape of a cone in 3D; Fig 15E) of the source layer (Upper and/or lower source-level semiconductor layer; 116/112; Fig 15E; ¶[0060]).
Re Claim 8, Miyake teaches the semiconductor structure of Claim 7, wherein a lateral extent (Lateral width along vertical channel opening surrounded by 114; Fig 15E) of the opening (Memory opening; 49; Fig 9B; ¶[0106]) in the source-side spacer layer (Source contact layer; 114; Fig 15E; ¶[0143]) increases with a vertical distance (Lateral width of opening within 114 increases with vertical distance; Fig 15E) from a horizontal plane (Horizontal plane along intersection of 112/114; Fig 15E) including an interface between the source-side spacer layer and the source layer (Upper and/or lower source-level semiconductor layer; 116/112; Fig 15E; ¶[0060]) toward the alternating stack (Alternating stack; 132/242; Figs 9B/24; ¶[0161]).
Re Claim 9, Miyake teaches the semiconductor structure of Claim 7, wherein the tapered conical sidewall (Surfaces of 61T/61L/61B/61P are tapered and conical (annular); Fig 15E; ¶[0153]) comprises a second tapered conical surface segment (Segment from 61T to 61S; Fig 15E) that contacts a conical surface segment (Segment of memory film 50 along 61T to 61S; Fig 15E) of an outer sidewall (Sidewall of 50; Fig 15E) of the memory film (Blocking dielectric/Charge storage/Tunneling dielectric; 52/54/56; Fig 15E; ¶[0114]).
Re Claim 10, Miyake teaches the semiconductor structure of Claim 2, wherein:
the semiconductor source cap structure (Source region; 61; Fig 15E; ¶[0147]) further comprises a cylindrical surface segment (Tubular/lateral-protrusion segments; 61T/61L; Fig 15E; ¶[0153]); and
the first end surface segment (Bottom segment; 61B; Fig 15E; ¶[0153]) is adjoined to a first periphery (Lateral-protrusion segment (right side); 61L; Fig 15E; ¶[0153]) of the cylindrical surface segment.
Re Claim 11, Miyake teaches the semiconductor structure of Claim 10, further comprising an annular semiconductor ring (Source contact layer upper portions surrounding 61T to 61L; 114; Fig 15E; ¶[0143]) having an inner cylindrical surface (Inner surface of curved portions of 114; Fig 15E) that contacts a first cylindrical area (Surface area of lower portion of 61T to 61L; Fig 15E) of the cylindrical surface segment (Tubular/lateral-protrusion segments; 61T/61L; Fig 15E; ¶[0153]) of the semiconductor source cap structure (Source region; 61; Fig 15E; ¶[0147]) .
Re Claim 12, Miyake teaches the semiconductor structure of Claim 11, wherein:
a second cylindrical area (Surface area of 61T adjacent to memory film 50; Fig 15E) of the cylindrical surface segment (Tubular/lateral-protrusion segments; 61T/61L; Fig 15E; ¶[0153]) of the semiconductor source cap structure (Source region; 61; Fig 15E; ¶[0147]) contacts a cylindrical surface segment (Cylindrical surface area of memory film 50; Fig 15E) of an inner sidewall (Inner sidewall of 50) of the memory film (Blocking dielectric/Charge storage/Tunneling dielectric; 52/54/56; Fig 15E; ¶[0114]); and
the memory film comprises an annular plate portion (Annular portion on sidewalls of 61T; Fig 15E) that is interposed between the source-side spacer layer (Source contact layer; 114; Fig 15E; ¶[0143]) and the annular semiconductor ring (Source contact layer upper portions surrounding 61T to 61L; 114; Fig 15E; ¶[0143]) .
Re Claim 13, Miyake teaches the semiconductor structure of Claim 10, wherein:
the semiconductor source cap structure (Source region; 61; Fig 15E; ¶[0147]) further comprises second end surface segment (Convex annular surface/Tubular segment; 61S/61T; Fig 15E; ¶[0152]) that is adjoined to a second periphery (Lateral-protrusion segment (left side); 61L; Fig 15E; ¶[0153]) of the cylindrical surface segment (Tubular/lateral-protrusion segments; 61T/61L; Fig 15E; ¶[0153]); and
the second end surface segment comprises a convex surface segment (Convex portion of 61S; Fig 15E) that contacts a concave surface segment (Concave portion of 60 in contact with convex portion of 61S; Fig 15E) of the vertical semiconductor channel (Semiconductor channel material layer; 60/60L; Fig 15E; ¶[0115]).
Re Claim 14, Miyake teaches the semiconductor structure of Claim 10, wherein:
the semiconductor source cap structure (Source region; 61; Fig 15E; ¶[0147]) has a variable thickness (Thickness which changes vertically; Fig 15E) that varies along a radial direction (Radially from center of 162 outwards to edge of 61; Fig 15E) from a vertical axis (Vertical axis; Fig 15E) passing through a geometrical center (Located in the center of 162; Fig 15E) of the semiconductor source cap structure; and
the semiconductor source cap structure further comprises a central seam (Silicate glass layer; 162L; Fig 15E; ¶[0116]) that vertically extends from the first end surface segment (Bottom segment; 61B; Fig 15E; ¶[0153]) to a second end surface segment (Convex annular surface/Tubular segment; 61S/61T; Fig 15E; ¶[0152]) that is adjoined to a second periphery (Lateral-protrusion segment (left side); 61L; Fig 15E; ¶[0153]) of the cylindrical surface segment (Tubular/lateral-protrusion segments; 61T/61L; Fig 15E; ¶[0153]) .
Re Claim 15, Miyake teaches the semiconductor structure of Claim 2, wherein:
the vertical semiconductor channel (Semiconductor channel material layer; 60/60L; Fig 15E; ¶[0115]) has a doping of a first conductivity type (Doped with p-type; ¶¶[0060, 0115]);
the source-side spacer layer (Source contact layer; 114; Fig 15E; ¶[0143]) comprises a semiconductor material layer (Semiconductor material; ¶[0143]);
the semiconductor source cap structure (Source region; 61; Fig 15E; ¶[0147]) comprises a semiconductor material having a doping of a second conductivity type (Semiconductor material that is n-doped; ¶¶[0060, 0147]) that is an opposite of the first conductivity type;
a first end (Bottom end of 60; Fig 15E) of the vertical semiconductor channel contacts the semiconductor source cap structure; and
the memory opening fill structure (Blocking dielectric/Charge storage/Tunneling dielectric; 52/54/56; Semiconductor channel material layer; 60/60L; Source region; 61; Dielectric core; 62; Drain region; 63; Fig 15E; ¶¶[0112 - 0115, 0122, 0124]) further comprises a drain region (Drain region; 63; Fig 15E; ¶[0124]) having a doping of the second conductivity type (¶[0124]) and contacting a second end (Upper end of 60; Fig 15E) of the vertical semiconductor channel opposite to the first end.
7. Claims 16-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Okina, Teruo et al. (Pub No. US 20230284443 A1) (hereinafter, Okina).
Re Claim 16, Okina teaches a method of forming a semiconductor structure, comprising:
forming a source-side spacer layer (Semiconductor material layer; 14; Fig 1; ¶[0057]) over a carrier substrate (9; Fig 1; ¶[0057]);
Okina, Fig 1: Forming alternating stack over source layer and carrier substrate
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forming an alternating stack (Alternating stack; 32/42; Fig 1; ¶[0057]) of insulating layers (First material layers; 32; Fig 1; ¶[0057]) and spacer material layers (Second material layers; 42; Fig 1; ¶[0057]) over the source-side spacer layer, wherein the spacer material layers are formed as or are subsequently replaced with electrically conductive layers (46; Fig 9; ¶[0105]);
forming a memory opening (49; Fig 3A; ¶[0072]) through the alternating stack and the source-side spacer layer;
Okina, Fig 3A: Forming memory openings within alternating stack and source layers
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forming a memory film (50; Fig 4; ¶[0078]) at a peripheral portion (Sidewalls of opening 49; Fig 4; ¶[0078]) of the memory opening;
Okina, Fig 4: Forming memory film and semiconductor channel material layer
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forming a semiconductor source cap structure (Semiconductor pillar portion; 60P; Fig 6; ¶[0092]) at a bottom portion (Bottom of memory film 50; Fig 6) of the memory film;
Okina, Fig 6: Forming source cap structure over channel
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forming a vertical semiconductor channel (Vertical semiconductor channel/semiconductor channel material layer; 60/60L; Fig 6; ¶¶[0083,0091]) on a top surface (Top surface of 60P; Fig 6) of the semiconductor source cap structure and on an inner sidewall (Inner sidewall of 50; Fig 6) of the memory film;
removing the carrier substrate (Removing carrier substrate from top of 12; Figs 14B-15; ¶[0122]); and
Okina, Figs 14B-15: Removing carrier substrate from 3D memory device
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forming a source layer (Metallic material layer; 123L; Fig 20; ¶[0130]; Note: May also be Polysilicon) on an exposed bottom surface segment (Upper surface of 60P; Fig 20) of the semiconductor source cap structure.
Okina, Fig 20: Forming source layer over bottom surface segment of source cap structure
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Re Claim 17, Okina teaches the method of Claim 16, wherein:
the memory opening (49; Fig 3A; ¶[0072]) comprises a bottom cavity portion (Cavity portion within 14; Fig 3A) having a shape of an inverted cone or an inverted conical frustum (Conical frustum; Fig 3A); and
the semiconductor source cap structure (Semiconductor pillar portion; 60P; Fig 6; ¶[0092]) is formed by conformally depositing and isotropically etching (Isotropic etch process performed on 60P; Fig 29; ¶[0150]) a doped semiconductor material (Doped with first or second conductivity type; ¶[0151]), wherein a remaining portion of the doped semiconductor material (The remaining portion of 60P which is etched; ¶[0150]) comprises the semiconductor source cap structure.
Re Claim 18, Okina teaches the method of Claim 16, wherein:
the vertical semiconductor channel (Vertical semiconductor channel/semiconductor channel material layer; 60/60L; Fig 6; ¶¶[0083,0091]; Note: Per ¶[0088] Semiconductor channel material layer 60L is planarized and remaining portions are the vertical semiconductor channel 60) comprises dopants of a first conductivity type (Doping may be p-type or n-type; ¶[0083]) at a first atomic concentration (Range between 1.0 × 10.sup.14/cm.sup.3 to 1.0 × 10.sup.18/cm.sup.3; ¶[0083]); and
the semiconductor source cap structure (Semiconductor pillar portion; 60P; Fig 6; ¶[0092]) comprises dopants of a second conductivity type (Doped with first or second conductivity type; ¶[0151]) that is an opposite of the first conductivity type at a second atomic concentration that is higher (Concentration of 60P may be higher doping concentration than 60; ¶[0151]) than the first atomic concentration.
Re Claim 19, Okina teaches the method of Claim 16, further comprising:
forming a backside stopper layer (Dielectric spacer layer; 12; Fig 1; ¶[0057]) over the carrier substrate (9; Fig 1; ¶[0057]), wherein the source-side spacer layer (Semiconductor material layer; 14; Fig 1; ¶[0057]) is formed over the backside stopper layer;
forming an annular recess cavity (Cylindrical recess in bottom of opening 49 within 12; Fig 3A) around the memory opening (49; Fig 3A; ¶[0072]) at a level (Annular recess cavity is formed within 12; Fig 3A) of the backside stopper layer;
forming an annular semiconductor ring (Vertical channel/semiconductor channel material layer; 60/60L; Fig 4; ¶[0083]) in the annular recess cavity; and
performing a selective semiconductor deposition process (Optional process of recrystallizing vertical channels 60 to grow pillar portions 60P through irradiation with a laser; ¶[0152]) that grows a semiconductor material (Material comprising pillar portion 60P, i.e. Polysilicon; ¶[0152]) from a physically exposed surface (Surfaces of 60; ¶[0152]) of the annular semiconductor ring, wherein the semiconductor source cap structure (Semiconductor pillar portion; 60P; Fig 6; ¶[0092]) comprises a portion (A portion of material comprising pillar portion 60P; ¶[0152]) of the semiconductor material.
Re Claim 20, Okina teaches the method of Claim 19, wherein:
the carrier substrate (9; Fig 1; ¶[0057]) is removed employing a planarization process or an etch process (Isotropic wet etch process etches material of carrier substrate 9; ¶[0122]) that employs the backside stopper layer (Dielectric spacer layer; 12; Fig 1; ¶[0057]) as a stopping layer (Dielectric spacer 12 acts as a stopper during wet etch process such that carrier substrate has an etch selectivity to dielectric spacer 12; ¶[0122]);
the method further comprises removing a physically exposed portion (Removing portions of memory film 50 and dielectric spacer 12; Fig 19A; ¶[0126]) of the memory film (50; Fig 19A; ¶[0126]) and the backside stopper layer; and
Okina, Fig 19A: Removing exposed portion of memory film and backside stopper layer
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the source layer (Metallic material layer; 123L; Fig 20; ¶[0130]) is formed on a bottom surface (123L is formed over upper surface of 14; Fig 20) of the source-side spacer layer (Semiconductor material layer; 14; Fig 2; ¶[0057]) and on an exposed cylindrical sidewall of a remaining portion (Cylindrical sidewall of pillar cavity 107; Figs 19B-20; ¶[0127]) of the memory film after removal of the physically exposed portion of the memory film.
Okina, Fig 20: Forming source-side spacer layer over memory film
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Claim Rejections - 35 USC § 103
8. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
9. Claims 4 and 6 are rejected under 35 U.S.C. 103 as being unpatentable over Miyake, Daisuke et al. (Pub No. US 20210265379 A1) (hereinafter, Miyake) as applied to claims 3 and 5 above, and further in view of Okina, Teruo et al. (Pub No. US 20230284443 A1) (hereinafter, Okina).
Re Claim 4, Miyake teaches the semiconductor structure of Claim 3, wherein the annular conical surface segment comprises:
a second tapered annular area (Convex annular surface; 61S; Fig 15E; ¶[0152]) in contact with the memory film (Blocking dielectric/Charge storage/Tunneling dielectric; 52/54/56; Fig 15E; ¶[0114]).
However, Miyake does not teach a first tapered annular area in contact with the source layer.
In the same field of endeavor, Okina teaches a first tapered annular area (Surface area in shape of a conical frustum of channel 60 connected to 60P; Fig 20) in contact with the source layer (Metallic material layer; 123L; Fig 20; ¶[0130]).
Accordingly, it would have been obvious for a person having ordinary skill in the art before the effective filing date of the invention to have combined a first tapered annular area in contact with the source layer, as taught by Okina, with the semiconductor device as taught by Miyake. One would have been motivated to do this with a reasonable expectation of success because a direct connection between the source cap structure and the source region is advantageous over the 3-layer connection of the source cap structure, source layer and source region, such that higher integration density in the 3D semiconductor device may be obtained.
Re Claim 6, Miyake does not teach the semiconductor structure of Claim 5, wherein the second end surface segment comprises a convex surface segment located entirely between a first horizontal plane including a first horizontal surface of the source-side spacer layer and a second horizontal plane including a second horizontal surface of the source-side spacer layer. In the same field of endeavor, Okina teaches the semiconductor structure of Claim 5, wherein the second end surface segment (Segment of memory opening fill structure 58 in a conical frustum from lower to upper surface of semiconductor material layer 14; Fig 20) comprises a convex surface segment (Segment of memory opening fill structure 58 in a conical frustum from lower to upper surface of semiconductor material layer 14; Fig 20) located entirely between a first horizontal plane including a first horizontal surface (Upper surface of 14 taken as the first horizontal plane; Fig 20) of the source-side spacer layer (Semiconductor material layer; 14; Fig 2; ¶[0057]) and a second horizontal plane including a second horizontal surface (Lower surface of 14 taken as the second horizontal plane; Fig 20) of the source-side spacer layer.
Accordingly, it would have been obvious for a person having ordinary skill in the art before the effective filing date of the invention to have combined the second end surface segment comprising a convex surface segment located entirely between a first horizontal plane including a first horizontal surface of the source-side spacer layer and a second horizontal plane including a second horizontal surface of the source-side spacer layer, as taught by Onuki, with the semiconductor device as taught by Miyake. One would have been motivated to do this with a reasonable expectation of success because the electric field surrounding the second end surface segment of the memory fill structure is controlled within the surface area of the surrounding source-side spacer layer, reducing the fringing field effect and allowing for more efficient programming and reading operations.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
[1] Hinoue, Tatsuya et al. (Pub No. US 20210005627 A1) discloses first memory openings formed through a first alternating stack of first insulating layers and first spacer material layers. Each first memory opening is filled with a first memory film, a sacrificial dielectric liner, and a first-tier opening fill material portion. Second memory openings are formed through a second alternating stack of second insulating layers and second spacer material layers. A second memory film is formed in each second memory opening. The first-tier opening fill material portions are removed selective to the sacrificial dielectric liners. The sacrificial dielectric liners are removed selective to the second memory films and the first memory films. A vertical semiconductor channel can be formed on each vertical stack of a first memory film and a second memory film.
[2] Cui, Zhixin et al. (Pub No. US 11302714 B2) discloses a three-dimensional memory device includes a source contact layer overlying a substrate, an alternating stack of insulating layers and electrically conductive layers located overlying the source contact layer, and a memory opening fill structure located within a memory opening extending through the alternating stack and the source contact layer. The memory opening fill structure includes a composite semiconductor channel and a memory film laterally surrounding the composite semiconductor channel. The composite semiconductor channel includes a pedestal channel portion having controlled distribution of n-type dopants that diffuse from the source contact layer with a lower diffusion rate provided by carbon doping and smaller grain sizes, or has arsenic doping providing limited diffusion into the vertical semiconductor channel. The vertical semiconductor channel has large grain sizes to provide high charge carrier mobility, and is free of or includes only a low concentration of carbon atoms and n-type dopants therein.
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/T.E.D./
Examiner
Art Unit 2817
/ELISEO RAMOS FELICIANO/Supervisory Patent Examiner, Art Unit 2817