DETAILED ACTION
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
General Remarks
2. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection.
3. When responding to this office action, applicants are advised to provide the examiner with paragraph numbers in the application and/or references cited to assist the examiner in locating appropriate paragraphs.
4. Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable
interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
Response to Arguments
5. Applicant’s arguments, see Response to Rejections under 35 U.S.C. § 102 (a)(1), filed 5/18/2026, with respect to the rejection(s) of claim 1 under 35 U.S.C. § 102 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Miyake, Daisuke et al. (Pub No. US 20210265379 A1) (hereinafter, Miyake) in view of Sharangpani, Rahul et al. (Pub No. US 20240349501 A1) (hereinafter, Sharangpani).
6. Applicant’s arguments, see Response to Rejections under 35 U.S.C. § 102 (a)(1), filed 5/18/2026, with respect to the rejection(s) of claim 2 under 35 U.S.C. § 102 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Miyake, Daisuke et al. (Pub No. US 20210265379 A1) (hereinafter, Miyake) in view of Sharangpani, Rahul et al. (Pub No. US 20240349501 A1) (hereinafter, Sharangpani) in view of Okina, Teruo et al. (Pub No. US 20230284443 A1) (hereinafter, Okina).
7. Applicant’s arguments, see Response to Rejections under 35 U.S.C. § 102 (a)(1), filed 5/18/2026, with respect to the rejection of claim 13 have been fully considered and are persuasive. The rejection of claim 13 has been withdrawn.
8. Applicant’s arguments, see Response to Rejections under 35 U.S.C. § 102 (a)(1), filed 5/18/2026, with respect to the rejection(s) of claim 16 under 35 U.S.C. § 102 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Okina, Teruo et al. (Pub No. US 20230284443 A1) (hereinafter, Okina) in view of Sharangpani, Rahul et al. (Pub No. US 20240349501 A1) (hereinafter, Sharangpani).
9. Applicant’s arguments with respect to claims 4 and 6 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
For above mentioned reasons, the rejection is deemed proper and considered final.
Claim Rejections - 35 USC § 103
10. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
11. Claim 1 is rejected under 35 U.S.C. 103 as being unpatentable over Miyake, Daisuke et al. (Pub No. US 20210265379 A1) (hereinafter, Miyake), and further in view of Sharangpani, Rahul et al. (Pub No. US 20240349501 A1) (hereinafter, Sharangpani).
Re Claim 1, (Currently Amended) Miyake teaches a semiconductor structure, comprising:
an alternating stack (Alternating stack; 132/246; Figs 9B/24; ¶[0161]) of insulating layers (Insulating layers; 132; Fig 24; ¶[0070]) and electrically conductive layers (Electrically conductive/sacrificial layers; 142/242/246; Figs 9B/24; ¶[0161]);
Miyake, Fig 9B: Forming memory openings in alternating stack and source layers
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a memory opening (Memory opening; 49; Fig 9B; ¶[0106]) vertically extending through the alternating stack;
a memory opening fill structure (Blocking dielectric/Charge storage/Tunneling dielectric; 52/54/56; Semiconductor channel material layer; 60/60L; Source region; 61; Dielectric core; 62; Drain region; 63; Fig 15E; ¶¶[0112 - 0115, 0122, 0124]) located in the memory opening and comprising a memory film (Blocking dielectric/Charge storage/Tunneling dielectric; 52/54/56; Fig 15E; ¶[0114]), a vertical semiconductor channel (Semiconductor channel material layer; 60/60L; Fig 15E; ¶[0115]), and a semiconductor source cap structure (Source region; 61; Fig 15E; ¶[0147]) which is at least partially laterally surrounded by the memory film and which contacts the vertical semiconductor channel;
a source-side spacer layer (Source contact layer; 114; Fig 15E; ¶[0143]) laterally surrounding the memory opening fill structure, wherein the memory film comprises a vertically-extending portion (Vertically extending portion of memory film 50; Fig 15E) contacting the vertical semiconductor channel and the semiconductor source cap structure (Vertical portions of memory film 50 contact vertical channel 60/60L and source region 61; Fig 15); and
a source layer (Upper and/or lower source-level semiconductor layer; 116/112; Fig 15E; ¶[0060]) contacting at least a first end surface segment (Bottom segment; 61B; Fig 15E; ¶[0153]) of the semiconductor source cap structure.
Miyake, Fig 15E: 3D memory device with memory fill structures and source layers
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However, Miyake does not teach wherein the memory film comprises a horizontally-extending portion having a first horizontal surface contacting a horizontal surface of the source-side spacer layer.
In the same field of endeavor, Sharangpani teaches wherein the memory film (50; Fig 16F; ¶[0087]) comprises a horizontally-extending portion (Left side top horizontal portions of memory film; Fig 16F) having a first horizontal surface (Left side top horizontal surfaces of memory film; Fig 16F) contacting a horizontal surface (Bottom surface of metallic barrier liner 224B; Fig 16F) of the source-side spacer layer (Source contact structure; 224/224B; Fig 16F; ¶[0124]).
Sharangpani, Fig 16F: Cross-sectional view of formation of channel cap structure, includes a metallic barrier liner contacting a source cap structure
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Accordingly, it would have been obvious for a person having ordinary skill in the art before the effective filing date of the invention to have used memory film comprises a horizontally-extending portion having a first horizontal surface contacting a horizontal surface of the source-side spacer layer, as taught by Sharangpani, with the semiconductor device as taught by Miyake. One would have been motivated to do this with a reasonable expectation of success because the horizontal surfaces of the memory film and source-side spacer layer allow uniformity of carriers being injected from the source contact layer to the memory film, allowing for the memory block to be biased simultaneously across multiple memory cells in order to enhance erase operations.
12. Claims 2-12 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Miyake, Daisuke et al. (Pub No. US 20210265379 A1) (hereinafter, Miyake) in view of Sharangpani, Rahul et al. (Pub No. US 20240349501 A1) (hereinafter, Sharangpani), and further in view of Okina, Teruo et al. (Pub No. US 20230284443 A1) (hereinafter, Okina).
Re Claim 2, (Currently Amended) Miyake teaches the semiconductor structure of Claim 1, wherein:
The source-side spacer layer (Source contact layer; 114; Fig 15E; ¶[0143]) located between the source layer (Upper and/or lower source-level semiconductor layer; 116/112; Fig 15E; ¶[0060]) and the alternating stack (Alternating stack; 132/246; Figs 9B/24; ¶[0161]);
the memory opening (Memory opening; 49; Fig 9B; ¶[0106]) also vertically extends through (49 extends through 116; Fig 9B) the source-side spacer layer;
the vertically-extending portion (Vertically extending portion of memory film 50; Fig 15E) of the memory film (Blocking dielectric/Charge storage/Tunneling dielectric; 52/54/56; Fig 15E; ¶[0114]) further contacts the source-side spacer layer (Source contact layer; 114; Fig 15E; ¶[0143]), and
the semiconductor source cap structure (Source region; 61; Fig 15E; ¶[0147]) is laterally surrounded by the source-side spacer layer.
However, Miyake in view of Sharangpani does not teach the memory film laterally separates the source-side spacer layer from both the vertical semiconductor channel and the semiconductor source cap structure;
In the same field of endeavor, Okina teaches the memory film (50; Fig 22B; ¶[0084]) laterally separates the source-side spacer layer (Semiconductor material layer; 14; Fig 22B; ¶[0057]) from both the vertical semiconductor channel (60; Fig 22B; ¶[0089]) and the semiconductor source cap structure (Semiconductor pillar portion; 60P; Fig 22B; ¶[0092]).
Accordingly, it would have been obvious for a person having ordinary skill in the art before the effective filing date of the invention to have used memory film which laterally separates the source-side spacer layer from both the vertical semiconductor channel and the semiconductor source cap structure, as taught by Okina, with the semiconductor device as taught by Miyake in view of Sharangpani. One would have been motivated to do this with a reasonable expectation of success in order to prevent short-circuiting between the semiconductor cap structure, vertical channel and source-side spacer layer, rendering a loss of functionality at the junction between the semiconductor cap structure and vertical channel.
Re Claim 3, (Original) Miyake teaches the semiconductor structure of Claim 2, wherein:
the semiconductor source cap structure (Source region; 61; Fig 15E; ¶[0147]) further comprises an annular conical surface segment (Convex annular surface/Tubular segment; 61S/61T; Fig 15E; ¶[0152]) adjoined to the first end surface segment (Bottom segment; 61B; Fig 15E; ¶[0153]); and
the annular conical surface segment is laterally surrounded by the memory film (Blocking dielectric/Charge storage/Tunneling dielectric; 52/54/56; Fig 15E; ¶[0114]) and by the source-side spacer layer (Source contact layer; 114; Fig 15E; ¶[0143]).
Re Claim 4, (Original) Miyake teaches the semiconductor structure of Claim 3, wherein the annular conical surface segment comprises:
a second tapered annular area (Convex annular surface; 61S; Fig 15E; ¶[0152]) in contact with the memory film (Blocking dielectric/Charge storage/Tunneling dielectric; 52/54/56; Fig 15E; ¶[0114]).
However, Miyake in view of Sharangpani does not teach a first tapered annular area in contact with the source layer.
In the same field of endeavor, Okina teaches a first tapered annular area (Surface area in shape of a conical frustum of channel 60 connected to 60P; Fig 20) in contact with the source layer (Metallic material layer; 123L; Fig 20; ¶[0130]).
Accordingly, it would have been obvious for a person having ordinary skill in the art before the effective filing date of the invention to have combined a first tapered annular area in contact with the source layer, as taught by Okina, with the semiconductor device as taught by Miyake in view of Sharangpani. One would have been motivated to do this with a reasonable expectation of success because a direct connection between the source cap structure and the source region is advantageous over the 3-layer connection of the source cap structure, source layer and source region, such that higher integration density in the 3D semiconductor device may be obtained.
Re Claim 5, (Currently Amended) Miyake teaches the semiconductor structure of Claim 3, wherein the semiconductor source cap structure (Source region; 61; Fig 15E; ¶[0147]) further comprises a second end surface segment (Convex annular surface/Tubular segment; 61S/61T; Fig 15E; ¶[0152]) that contacts the end surface (End surface of 60 in contact with 61S; Fig 15E) of the vertical semiconductor channel (Semiconductor channel material layer; 60/60L; Fig 15E; ¶[0115]).
Re Claim 6, (Original) Miyake in view of Sharangpani does not teach the semiconductor structure of Claim 5, wherein the second end surface segment comprises a convex surface segment located entirely between a first horizontal plane including a first horizontal surface of the source-side spacer layer and a second horizontal plane including a second horizontal surface of the source-side spacer layer.
In the same field of endeavor, Okina teaches the semiconductor structure of Claim 5, wherein the second end surface segment (Segment of memory opening fill structure 58 in a conical frustum from lower to upper surface of semiconductor material layer 14; Fig 20) comprises a convex surface segment (Segment of memory opening fill structure 58 in a conical frustum from lower to upper surface of semiconductor material layer 14; Fig 20) located entirely between a first horizontal plane including a first horizontal surface (Upper surface of 14 taken as the first horizontal plane; Fig 20) of the source-side spacer layer (Semiconductor material layer; 14; Fig 2; ¶[0057]) and a second horizontal plane including a second horizontal surface (Lower surface of 14 taken as the second horizontal plane; Fig 20) of the source-side spacer layer.
Accordingly, it would have been obvious for a person having ordinary skill in the art before the effective filing date of the invention to have combined the second end surface segment comprising a convex surface segment located entirely between a first horizontal plane including a first horizontal surface of the source-side spacer layer and a second horizontal plane including a second horizontal surface of the source-side spacer layer, as taught by Onuki, with the semiconductor device as taught by Miyake in view of Sharangpani. One would have been motivated to do this with a reasonable expectation of success because the electric field surrounding the second end surface segment of the memory fill structure is controlled within the surface area of the surrounding source-side spacer layer, reducing the fringing field effect and allowing for more efficient programming and reading operations.
Re Claim 7, (Original) Miyake teaches the semiconductor structure of Claim 3, wherein:
the source-side spacer layer (Source contact layer; 114; Fig 15E; ¶[0143]) comprises an opening (Opening surrounding 50/53/61T/61L/61B/61P; Fig 15E) having a tapered conical sidewall (Surfaces of 61T/61L/61B/61P are tapered and conical (annular); Fig 15E; ¶[0153]); and
the tapered conical sidewall comprises a first tapered conical surface segment (Segment from 61L upwards towards edge of 53; Fig 15E) that contacts a conical surface segment (Sidewalls of 116; i.e. in shape of a cone in 3D; Fig 15E) of the source layer (Upper and/or lower source-level semiconductor layer; 116/112; Fig 15E; ¶[0060]).
Re Claim 8, (Original) Miyake teaches the semiconductor structure of Claim 7, wherein a lateral extent (Lateral width along vertical channel opening surrounded by 114; Fig 15E) of the opening (Memory opening; 49; Fig 9B; ¶[0106]) in the source-side spacer layer (Source contact layer; 114; Fig 15E; ¶[0143]) increases with a vertical distance (Lateral width of opening within 114 increases with vertical distance; Fig 15E) from a horizontal plane (Horizontal plane along intersection of 112/114; Fig 15E) including an interface between the source-side spacer layer and the source layer (Upper and/or lower source-level semiconductor layer; 116/112; Fig 15E; ¶[0060]) toward the alternating stack (Alternating stack; 132/242; Figs 9B/24; ¶[0161]).
Re Claim 9, (Original) Miyake teaches the semiconductor structure of Claim 7, wherein the tapered conical sidewall (Surfaces of 61T/61L/61B/61P are tapered and conical (annular); Fig 15E; ¶[0153]) comprises a second tapered conical surface segment (Segment from 61T to 61S; Fig 15E) that contacts a conical surface segment (Segment of memory film 50 along 61T to 61S; Fig 15E) of an outer sidewall (Sidewall of 50; Fig 15E) of the memory film (Blocking dielectric/Charge storage/Tunneling dielectric; 52/54/56; Fig 15E; ¶[0114]).
Re Claim 10, (Original) Miyake teaches the semiconductor structure of Claim 2, wherein:
the semiconductor source cap structure (Source region; 61; Fig 15E; ¶[0147]) further comprises a cylindrical surface segment (Tubular/lateral-protrusion segments; 61T/61L; Fig 15E; ¶[0153]); and
the first end surface segment (Bottom segment; 61B; Fig 15E; ¶[0153]) is adjoined to a first periphery (Lateral-protrusion segment (right side); 61L; Fig 15E; ¶[0153]) of the cylindrical surface segment.
Re Claim 11, (Currently Amended) Miyake teaches the semiconductor structure of Claim 10, further comprising an annular semiconductor ring (Source contact layer upper portions surrounding 61T to 61L; 114; Fig 15E; ¶[0143]) having an inner cylindrical surface (Inner surface of curved portions of 114; Fig 15E) that contacts a first cylindrical area (Surface area of lower portion of 61T to 61L; Fig 15E) of the cylindrical surface segment (Tubular/lateral-protrusion segments; 61T/61L; Fig 15E; ¶[0153]) of the semiconductor source cap structure (Source region; 61; Fig 15E; ¶[0147]).
However, Miyake does not teach an annular semiconductor ring having an inner cylindrical surface that contacts a second horizontal surface of the horizontally-extending portion of the memory film.
In the same field of endeavor, Sharangpani teaches an annular semiconductor ring (Metallic barrier liner; 224B; Fig 16F; ¶[0124]; Note: Per ¶[0124] 224B may be formed on physically exposed end surfaces of the memory film 50, creating a cylindrical surface from the plan view) having an inner cylindrical surface (Cylindrical surface in an embodiment of metallic barrier liner 224B, i.e. located above 49 in Fig 20B; Figs 16F/20B) that contacts a second horizontal surface (Horizontal top surface of memory film 50; Fig 16F) of the horizontally-extending portion (Horizontally extending portions of memory film 50; Fig 16F) of the memory film (50; Fig 16F; ¶[0087]).
Accordingly, it would have been obvious for a person having ordinary skill in the art before the effective filing date of the invention to have used an annular semiconductor ring having an inner cylindrical surface that contacts a second horizontal surface of the horizontally-extending portion of the memory film, as taught by Sharangpani, with the semiconductor device as taught by Miyake. One would have been motivated to do this with a reasonable expectation of success because the horizontal surfaces of the memory film and source-side spacer layer allow uniformity of carriers being injected from the source contact layer to the memory film, allowing for the memory block to be biased simultaneously across multiple memory cells in order to enhance erase operations.
Re Claim 12, (Currently Amended) Miyake teaches the semiconductor structure of Claim 11, wherein:
a second cylindrical area (Surface area of 61T adjacent to memory film 50; Fig 15E) of the cylindrical surface segment (Tubular/lateral-protrusion segments; 61T/61L; Fig 15E; ¶[0153]) of the semiconductor source cap structure (Source region; 61; Fig 15E; ¶[0147]) contacts a cylindrical surface segment (Cylindrical surface area of memory film 50; Fig 15E) of an inner sidewall (Inner sidewall of 50) of the memory film (Blocking dielectric/Charge storage/Tunneling dielectric; 52/54/56; Fig 15E; ¶[0114]); and
the memory film comprises an annular plate portion (Annular portion on sidewalls of 61T; Fig 15E) that is interposed between the source-side spacer layer (Source contact layer; 114; Fig 15E; ¶[0143]) and the annular semiconductor ring (Source contact layer upper portions surrounding 61T to 61L; 114; Fig 15E; ¶[0143]).
And the annular semiconductor ring contacts a sidewall (Sidewalls of tubular protrusions 61T; Fig 15E) of the semiconductor source cap structure (Source region/Tubular protrusion segments; 61/61T; Fig 15E; ¶[0147]; Note: Source region 61 may comprise of tubular protrusion segments 61T).
Re Claim 15, (Original) Miyake teaches the semiconductor structure of Claim 2, wherein:
the vertical semiconductor channel (Semiconductor channel material layer; 60/60L; Fig 15E; ¶[0115]) has a doping of a first conductivity type (Doped with p-type; ¶¶[0060, 0115]);
the source-side spacer layer (Source contact layer; 114; Fig 15E; ¶[0143]) comprises a semiconductor material layer (Semiconductor material; ¶[0143]);
the semiconductor source cap structure (Source region; 61; Fig 15E; ¶[0147]) comprises a semiconductor material having a doping of a second conductivity type (Semiconductor material that is n-doped; ¶¶[0060, 0147]) that is an opposite of the first conductivity type;
a first end (Bottom end of 60; Fig 15E) of the vertical semiconductor channel contacts the semiconductor source cap structure; and
the memory opening fill structure (Blocking dielectric/Charge storage/Tunneling dielectric; 52/54/56; Semiconductor channel material layer; 60/60L; Source region; 61; Dielectric core; 62; Drain region; 63; Fig 15E; ¶¶[0112 - 0115, 0122, 0124]) further comprises a drain region (Drain region; 63; Fig 15E; ¶[0124]) having a doping of the second conductivity type (¶[0124]) and contacting a second end (Upper end of 60; Fig 15E) of the vertical semiconductor channel opposite to the first end.
13. Claims 16-19 are rejected under 35 U.S.C. 103 as being unpatentable over Okina, Teruo et al. (Pub No. US 20230284443 A1) (hereinafter, Okina), and further in view of Sharangpani, Rahul et al. (Pub No. US 20240349501 A1) (hereinafter, Sharangpani).
Re Claim 16, (Currently Amended) Okina teaches a method of forming a semiconductor structure, comprising:
forming a source-side spacer layer (Semiconductor material layer; 14; Fig 1; ¶[0057]) over a carrier substrate (9; Fig 1; ¶[0057]);
Okina, Fig 1: Forming alternating stack over source layer and carrier substrate
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forming an alternating stack (Alternating stack; 32/42; Fig 1; ¶[0057]) of insulating layers (First material layers; 32; Fig 1; ¶[0057]) and spacer material layers (Second material layers; 42; Fig 1; ¶[0057]) over the source-side spacer layer, wherein the spacer material layers are formed as or are subsequently replaced with electrically conductive layers (46; Fig 9; ¶[0105]);
forming a memory opening (49; Fig 3A; ¶[0072]) through the alternating stack and the source-side spacer layer;
Okina, Fig 3A: Forming memory openings within alternating stack and source layers
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forming a memory film (50; Fig 4; ¶[0078]) at a peripheral portion (Sidewalls of opening 49; Fig 4; ¶[0078]) of the memory opening;
Okina, Fig 4: Forming memory film and semiconductor channel material layer
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forming a semiconductor source cap structure (Semiconductor pillar portion; 60P; Fig 6; ¶[0092]) at a bottom portion (Bottom of memory film 50; Fig 6) of the memory film;
Okina, Fig 6: Forming source cap structure over channel
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forming a vertical semiconductor channel (Vertical semiconductor channel/semiconductor channel material layer; 60/60L; Fig 6; ¶¶[0083,0091]) on a top surface (Top surface of 60P; Fig 6) of the semiconductor source cap structure and on an inner sidewall (Inner sidewall of 50; Fig 6) of the memory film;
removing the carrier substrate (Removing carrier substrate from top of 12; Figs 14B-15; ¶[0122]); and
Okina, Figs 14B-15: Removing carrier substrate from 3D memory device
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forming a source layer (Metallic material layer; 123L; Fig 20; ¶[0130]; Note: May also be Polysilicon) on an exposed bottom surface segment (Upper surface of 60P; Fig 20) of the semiconductor source cap structure.
Okina, Fig 20: Forming source layer over bottom surface segment of source cap structure
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However, Okina does not teach wherein the memory film comprises a vertically-extending portion and a horizontally-extending portion having a first horizontal surface contacting a horizontal surface of the source-side spacer layer.
In the same field of endeavor, Sharangpani teaches wherein the memory film (50; Fig 16F; ¶[0087]) comprises a vertically-extending portion (Portion of memory film 50 which vertically extends; Fig 16F) and a horizontally-extending portion (Top horizontal portions of memory film; Fig 16F) having a first horizontal surface (Top horizontal portions of memory film; Fig 16F) contacting a horizontal surface (Bottom surface of metallic barrier liner 224B; Fig 16F) of the source-side spacer layer (Source contact structure; 224/224B; Fig 16F; ¶[0124]).
Accordingly, it would have been obvious for a person having ordinary skill in the art before the effective filing date of the invention to have used memory film comprising a vertically-extending portion and a horizontally-extending portion having a first horizontal surface contacting a horizontal surface of the source-side spacer layer, as taught by Sharangpani, with the semiconductor device as taught by Miyake. One would have been motivated to do this with a reasonable expectation of success because the horizontal surfaces of the memory film and source-side spacer layer allow uniformity of carriers being injected from the source contact layer to the memory film, allowing for the memory block to be biased simultaneously across multiple memory cells in order to enhance erase operations. Further, the vertical portion of the memory film allows for electrical isolation between the source-side semiconducting layers and the vertical channel layer.
Re Claim 17, (Original) Okina teaches the method of Claim 16, wherein:
the memory opening (49; Fig 3A; ¶[0072]) comprises a bottom cavity portion (Cavity portion within 14; Fig 3A) having a shape of an inverted cone or an inverted conical frustum (Conical frustum; Fig 3A); and
the semiconductor source cap structure (Semiconductor pillar portion; 60P; Fig 6; ¶[0092]) is formed by conformally depositing and isotropically etching (Isotropic etch process performed on 60P; Fig 29; ¶[0150]) a doped semiconductor material (Doped with first or second conductivity type; ¶[0151]), wherein a remaining portion of the doped semiconductor material (The remaining portion of 60P which is etched; ¶[0150]) comprises the semiconductor source cap structure.
Re Claim 18, (Original) Okina teaches the method of Claim 16, wherein:
the vertical semiconductor channel (Vertical semiconductor channel/semiconductor channel material layer; 60/60L; Fig 6; ¶¶[0083,0091]; Note: Per ¶[0088] Semiconductor channel material layer 60L is planarized and remaining portions are the vertical semiconductor channel 60) comprises dopants of a first conductivity type (Doping may be p-type or n-type; ¶[0083]) at a first atomic concentration (Range between 1.0 × 10.sup.14/cm.sup.3 to 1.0 × 10.sup.18/cm.sup.3; ¶[0083]); and
the semiconductor source cap structure (Semiconductor pillar portion; 60P; Fig 6; ¶[0092]) comprises dopants of a second conductivity type (Doped with first or second conductivity type; ¶[0151]) that is an opposite of the first conductivity type at a second atomic concentration that is higher (Concentration of 60P may be higher doping concentration than 60; ¶[0151]) than the first atomic concentration.
Re Claim 19, (Currently Amended) Okina teaches the method of Claim 16, further comprising:
forming a backside stopper layer (Dielectric spacer layer; 12; Fig 1; ¶[0057]) over the carrier substrate (9; Fig 1; ¶[0057]), wherein the source-side spacer layer (Semiconductor material layer; 14; Fig 1; ¶[0057]) is formed over the backside stopper layer;
forming an annular recess cavity (Cylindrical recess in bottom of opening 49 within 12; Fig 3A) around the memory opening (49; Fig 3A; ¶[0072]) at a level (Annular recess cavity is formed within 12; Fig 3A) of the backside stopper layer;
performing a selective semiconductor deposition process (Optional process of recrystallizing vertical channels 60 to grow pillar portions 60P through irradiation with a laser; ¶[0152]) that grows a semiconductor material (Material comprising pillar portion 60P, i.e. Polysilicon; ¶[0152]) from a physically exposed surface (Surfaces of 60; ¶[0152]) of the annular semiconductor ring, wherein the semiconductor source cap structure (Semiconductor pillar portion; 60P; Fig 6; ¶[0092]) comprises a portion (A portion of material comprising pillar portion 60P; ¶[0152]) of the semiconductor material and contacts a sidewall (Sidewall of memory opening fill structure 58 comprising of semiconductor material layer 14; Fig 20) of the annular semiconductor ring (Memory opening fill structure 58 comprising of semiconductor material layer 14 surrounding 60P; Fig 20).
However, Okina does not teach forming an annular semiconductor ring in the annular recess cavity such that the annular semiconductor ring contacts a second horizontal surface of the horizontally-extending portion of the memory film.
In the same field of endeavor, Sharangpani teaches forming an annular semiconductor ring (Metallic barrier liner; 224B; Fig 16F; ¶[0124]; Note: Per ¶[0124] 224B may be formed on physically exposed end surfaces of the memory film 50, creating a cylindrical surface from the plan view) in the annular recess cavity (Cavity comprising of 224 surrounded by 32B; Fig 16F) such that the annular semiconductor ring contacts a second horizontal surface (Right side horizontal top surface of memory film 50; Fig 16F) of the horizontally-extending portion (Horizontally top surfaces of memory film 50; Fig 16F) of the memory film (50; Fig 16F; ¶[0087]).
Accordingly, it would have been obvious for a person having ordinary skill in the art before the effective filing date of the invention to have used an annular semiconductor ring in the annular recess cavity such that the annular semiconductor ring contacts a second horizontal surface of the horizontally-extending portion of the memory film, as taught by Sharangpani, with the semiconductor device as taught by Miyake. One would have been motivated to do this with a reasonable expectation of success because the horizontal surfaces of the memory film and source-side spacer layer allow uniformity of carriers being injected from the source contact layer to the memory film, allowing for the memory block to be biased simultaneously across multiple memory cells in order to enhance erase operations.
Allowable Subject Matter
14. Claims 13-14 and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
15. Regarding claim 13, the closest prior art Miyake, Daisuke et al. (Pub No. US 20210265379 A1) (hereinafter, Miyake) in view of Sharangpani, Rahul et al. (Pub No. US 20240349501 A1) (hereinafter, Sharangpani) either singularly or in combination fails to anticipate or render obvious
“The semiconductor structure of Claim 11, wherein the source layer contacts an end surface of the semiconductor source cap structure, a horizontal surface of the annular semiconductor ring, a sidewall of the annular semiconductor ring, a sidewall of the horizontally-extending portion of the memory film, and the source-side spacer layer,”
in combination with all other limitations in the claim(s) as claimed and defined by applicant.
In the instant case, re claim 13, Miyake discloses a source layer in contact with a source contact layer, however it is not in contact with an annular semiconductor ring or source cap structure. Sharangpani fails to cure the deficiencies of Miyake because Sharangpani discloses a source layer in contact with a semiconductor cap structure, however, not with a sidewall of an annular semiconductor ring or horizontally-extending portion of the memory film as illustrated in Fig. 40B of the instant application. Miyake in view of Sharangpani fails to contain a combination of elements which would yield a predictable result similar to the invention of claim 13.
16. Regarding claim 14, the closest prior art Miyake, Daisuke et al. (Pub No. US 20210265379 A1) (hereinafter, Miyake) in view of Okina, Teruo et al. (Pub No. US 20230284443 A1) (hereinafter, Okina) either singularly or in combination fails to anticipate or render obvious
“The semiconductor structure of Claim 10, wherein:
the semiconductor source cap structure has a variable thickness that varies along a radial direction from a vertical axis passing through a geometrical center of the semiconductor source cap structure; and
the semiconductor source cap structure further comprises a central seam that vertically extends from the first end surface segment to a second end surface segment that is adjoined to a second periphery of the cylindrical surface segment and contacts a concave surface segment of the vertical semiconductor channel,”
in combination with all other limitations in the claim(s) as claimed and defined by applicant.
In the instant case, re claim 14, Miyake discloses a semiconductor source cap structure in contact with said connecting elements of claim 14, however, Miyake does not disclose the limitation “a semiconductor source cape structure in contact with a concave surface segment of the vertical semiconductor channel.” The closest art to disclosing said limitation is Okina which discloses in Fig 22A, in its broadest reasonable interpretation, a semiconductor source cap structure in contact with a convex surface of a vertical semiconductor channel. Okina, however, does not disclose a concave surface segment of the vertical semiconductor channel in contact with any semiconductor material which may be considered a semiconductor source cap structure. Therefore, Miyake in view of Okina lack the prior art elements to yield predictable results similar to the invention of claim 14.
17. Regarding claim 20, the closest prior art Okina, Teruo et al. (Pub No. US 20230284443 A1) (hereinafter, Okina) in view of Sharangpani, Rahul et al. (Pub No. US 20240349501 A1) (hereinafter, Sharangpani) either singularly or in combination fails to anticipate or render obvious
“The method of Claim 19, wherein:
the carrier substrate is removed employing a planarization process or an etch process that employs the backside stopper layer as a stopping layer;
the method further comprises removing a physically exposed portion of the memory film and the backside stopper layer; and
the source layer is formed on an end surface of the semiconductor source cap structure, a horizontal surface of the annular semiconductor ring, a sidewall of the annular semiconductor ring, a sidewall of the horizontally-extending portion of the memory film, and the source-side spacer layer,”
in combination with all other limitations in the claim(s) as claimed and defined by applicant.
In the instant case, re claim 20, Okina discloses a source layer formed on an end surface of a semiconductor source cap structure, however, the source layer is not formed on a horizontal surface and a sidewall of the annular semiconductor ring according to claim 19. Sharangpani also fails to cure the deficiencies of Okina because Sharangpani does not disclose a source layer formed on a sidewall of a horizontally-extending portion of the memory film. Therefore, the prior art elements cannot be combined to yield predictable results similar to the invention of claim 20.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/T.E.D./
Examiner
Art Unit 2817
/ELISEO RAMOS FELICIANO/Supervisory Patent Examiner, Art Unit 2817
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