Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claim 6 objected to because of the following informalities: Claim 6 does not limit the structure claimed in claim 1. A graphical representation of device functionality is claimed. Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-6,10-12,19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Shan et al. ( US-20230402394-A1; Shan) in view of Matsui et al. (US 20070228427 A1; Matsui).
Regarding claim 1, Shan discloses a semiconductor memory device comprising: a substrate (Fig.14/19, 110; ¶26) ; a mold structure (Fig.14/19, 141/147; ¶30,54) including a plurality of gate electrodes (Fig.14/19, 141; ¶30,54) and a plurality of mold insulating films (Fig.14/19, 147; ¶43) alternately stacked on the substrate; and a channel structure (Fig.14/19, 150; ¶30,54) that penetrates the mold structure, wherein the channel structure comprises: a semiconductor pattern (Fig.14/19, 155; ¶46); and a dielectric film (Fig.14/19, 152/153/154; ¶44) on the semiconductor pattern, wherein the dielectric film comprises: a first crystalline film (Fig.14/19, 152; ¶44) that is in contact with the plurality of gate electrodes; and a second crystalline film (Fig.14/19, 154; ¶44) between the first crystalline film and the semiconductor pattern, wherein the first crystalline film includes a first matrix (hafnium oxide) …, wherein the second crystalline film includes a second matrix (hafnium oxide) …, wherein each of the first matrix and the second matrix comprises at least one of HfO2 (¶44) ,HfxZr1-402 (0.5<x<1), and Hfi-yZryO2 (0.5<y<1), but is silent on and wherein each of the first impurity and the second impurity has a concentration of 10 at% (atomic percent) or less of the first crystalline film and the second crystalline film, respectively.
Shan is silent on wherein the first crystalline film includes a first impurity, wherein the second crystalline film includes a second impurity, …and wherein each of the first impurity and the second impurity has a concentration of 10 at% (atomic percent) or less of the first crystalline film and the second crystalline film, respectively.
Matsui discloses a way to increase the dielectric constant of a HfO2 matrix by doping HfO2 with Yttrium oxide (¶12-13,22-27) at 5%. This stabilizes and raises the dielectric constant of crystalline HfO2.
Therefore, before the effective filing date it would have been obvious to one having ordinary skill in the art to dope the first and second crystalline films with an impurity less than 10 at% for forming higher dielectric constant insulation layers.
Regarding claim 2, Shan in view of Matsui discloses the semiconductor memory device of claim 1, wherein the first matrix (Fig.14/19, 152; ¶44 Hafnium Oxide Shan) includes a different material from that of the second matrix. (Fig.14/19, 154; ¶44 Silicon Nitride Shan)
Regarding claim 3, Shan in view of Matsui discloses the semiconductor memory device of claim 1, wherein each of the first impurity and the second impurity comprises A1203, SiO2, Y203 (¶12-13,22-27 Matsui), Er2O3, Lu2O3, Gd203, Ta20s, MgO, SiC, AIN, and/or Mo.
Therefore, before the effective filing date it would have been obvious to one having ordinary skill in the art to dope the first and second crystalline films with Y203 for forming higher dielectric constant insulation layers.
Regarding claim 4, Shan in view of Matsui discloses the semiconductor memory device of claim 3, wherein the first impurity (Y203 ¶12-13,22-27 Matsui) includes a different material from that of the second impurity (La203 ¶25 Matsui).
Therefore, before the effective filing date it would have been obvious to one having ordinary skill in the art to dope the first and second crystalline films with Y203 and La2O3 respectively for forming higher dielectric constant insulation layers with low leakage current.
Regarding claim 5, Shan in view of Matsui discloses the semiconductor memory device of claim 3, wherein the first impurity (Y203 ¶12-13,22-27 Matsui) and the second impurity (Y203 ¶12-13,22-27 Matsui)include a same material.
Therefore, before the effective filing date it would have been obvious to one having ordinary skill in the art to dope the first and second crystalline films with Y203 and Y2O3 respectively for forming higher dielectric constant insulation layers with low leakage current.
Regarding claim 6, Shan in view of Matsui discloses the semiconductor memory device of claim 1, wherein a polarization-hysteresis curve (P-V curve) of the dielectric film comprises a first curve and a second curve, wherein the first curve has a first slope at a first voltage in quadrant IV, a second slope at a second voltage in the quadrant IV or quadrant I, and a third slope at a third voltage in the quadrant I, wherein the second curve has a fourth slope at a fourth voltage in quadrant II, a fifth slope at a fifth voltage in the quadrant II or quadrant III, and a sixth slope at a sixth voltage in the quadrant III, wherein the second voltage is higher than the first voltage, and the third voltage is higher than the first and second voltages, wherein the fifth voltage is lower than the fourth voltage, and the sixth voltage is lower than the fourth and fifth voltages, wherein the second slope is less than the first slope, and the third slope is greater than the second slope, wherein the fifth slope is less than the fourth slope, and the sixth slope is greater than the fifth slope, and wherein the first curve and the second curve are spaced apart from an origin point.
The claim does not limit the structure but uses graphical representations to depict how the claimed device functions.
Regarding claim 10, Shan in view of Matsui discloses the semiconductor memory device of claim 1, further comprising an interfacial film (Fig.14/19,layer adjacent to semiconductor layer in stack 154; ¶44) between the dielectric film (Fig.14/19, 152/153/154; ¶44) and the semiconductor pattern. (Fig.14/19, 155; ¶46)
Shan discloses the layer 154 comprises multiple layers. The layer adjacent to the semiconductor pattern acts as an interfacial layer.
Regarding claim 11, Shan in view of Matsui discloses the semiconductor memory device of claim 10, wherein the interfacial film (Fig.14/19,layer adjacent to semiconductor layer in stack 154; ¶44) comprises silicon oxide (SiO2) (¶44).
Regarding claim 12, Shan in view of Matsui discloses the semiconductor memory device of claim 1, further comprising a source layer (161/162 through 131) in contact with the semiconductor pattern. (Fig.14/19, 155; ¶46)
Regarding claim 19, Shan discloses an electronic system comprising: a main board (Fig. 27, of memory card 400;¶88) ; a semiconductor memory device (Fig. 27, 402;¶88) on the main board; and a controller (Fig. 27, 404;¶88) on the main board, wherein the controller is electrically connected to the semiconductor memory device (must be for the device to work), wherein the semiconductor memory device comprises: a cell substrate (Fig.14/19, 110; ¶26) comprising a cell array region and an extension region; a mold structure (Fig.14/19, 141/147; ¶30,54) comprising a plurality of gate electrodes (Fig.14/19, 141; ¶30,54) that are sequentially stacked on the cell substrate and stacked in the extension region in a stepped manner; and a channel structure (Fig.14/19, 150; ¶30,54) that penetrates the mold structure in the cell array region, wherein the channel structure comprises a semiconductor pattern (Fig.14/19, 155; ¶46) and a dielectric film (Fig.14/19, 152/153/154; ¶44) on the semiconductor pattern, wherein the dielectric film comprises a first crystalline film (Fig.14/19, 152; ¶44) and a second crystalline film (Fig.14/19, 154; ¶44) between the first crystalline film and the semiconductor pattern, wherein the first crystalline film is in contact with the plurality of gate electrodes, wherein the first crystalline film includes a first matrix and the second crystalline film includes a second matrix, wherein each of the first matrix and the second matrix comprises at least one of HfO2 (¶44),HfxZri-xO2(O.5<x<1), and HfI-yZryO2(O.5<y<l), but is silent on wherein the first crystalline film has 10 at% (atomic percent) or less of a first impurity, wherein the second crystalline film has 10 at% or less of a second impurity, and wherein each of the first impurity and the second impurity comprises Al203, SiO2,Y203, Er2O3, Lu2O3, Gd2O3, Ta2 MgO, SiC, AIN, and/or Mo.
Matsui discloses a way to increase the dielectric constant of a HfO2 matrix by doping HfO2 with Yttrium oxide (¶12-13,22-27) at 5%. This stabilizes and raises the dielectric constant of crystalline HfO2.
Therefore, before the effective filing date it would have been obvious to one having ordinary skill in the art to dope the first and second crystalline films with an impurity less than 10 at% for forming higher dielectric constant insulation layers.
Claim(s) 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Shan et al. ( US-20230402394-A1; Shan) in view of Matsui et al. (US 20070228427 A1; Matsui) and further in view of Heo et al. ( US-20210359101-A1; Heo).
Regarding claim 7, Shan in view of Matsui discloses the semiconductor memory device of claim 1, but is silent on wherein the first crystalline film comprises a ferroelectric material and the second crystalline film comprises an antiferroelectric material.
Heo discloses forming a memory structure using both Ferroelectric and Antiferroelectric material. (Fig. 15, 21/22; ¶83)
Before the effective filing date of the invention it would have been obvious to one having ordinary skill in the art to use a ferroelectric material and an antiferroelectric material for the first and second crystalline films for producing optimal breakdown voltage.
Claim(s) 8-9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Shan et al. ( US-20230402394-A1; Shan) in view of Matsui et al. (US 20070228427 A1; Matsui) and further in view of Harari et al. ( US-20070051998-A1; Harari).
Regarding claim 8, Shan in view of Matsui discloses the semiconductor memory device of claim 1, but is silent on wherein the dielectric film further comprises an amorphous film between the first crystalline film and the second crystalline film.
Harari discloses a forming a dielectric structure where the middle layer is amorphous (Fig. 1, 50; ¶32 HfO.sub.2/Al.sub.2O.sub.3/HfO.sub.2)
Before the effective filing date of the invention it would have been obvious to one having ordinary skill in the art to use an amorphous layer between the crystalline films for producing a dielectric layer with the optimal high-k dielectric.
Regarding claim 9, Shan in view of Matsui discloses the semiconductor memory device of claim1, but is silent on wherein a thickness of the dielectric film is 150 angstroms (A) or less in a first direction parallel to an upper surface of the substrate.
Harari discloses a dielectric film having a thickness of about 100 .ANG (Fig.1, adding the thickness of 10/20/30; ¶29-31)
Before the effective filing date of the invention it would have been obvious to one having ordinary skill in the art to make the dielectric film 150 angstroms (A) or less to achieve reduction of device size.
Allowable Subject Matter
Claims 13-18 are allowed.
The following is an examiner’s statement of reasons for allowance, which paraphrases and summarizes the claimed invention without intending to be limiting, wherein the legally defined scope of the claimed invention is defined by the allowed claims themselves in view of the written description under 35 USC 112. This statement is not intended to necessarily state all the reasons for allowance or all the details why the claims are allowed and has not been written to specifically or impliedly state that all the reasons for allowance are set forth (MPEP 1302.14).
Regarding claim 13, the references of the Prior Art of record and considered pertinent to the applicant's disclosure and to the examiner’s knowledge does not teach or render obvious, at least to the skilled artisan, the instant invention regarding: " wherein a first matrix of the amorphous film comprises HfO2 and/or ZrO2, and wherein the first material comprises Al203 and/or SiO2.”, as recited in Claim 13, with the remaining features.
Claim 20 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The most relevant art discloses an amorphous Al2O3 layer but is silent on an amorphous HfO2 or ZrO2 matrix comprising an Al2O3 or SiO2 material.
Regarding claim 20, the references of the Prior Art of record and considered pertinent to the applicant's disclosure and to the examiner’s knowledge does not teach or render obvious, at least to the skilled artisan, the instant invention regarding: " wherein a matrix of the amorphous film comprises HfO2 and/or ZrO2,wherein the amorphous film comprises a first material, wherein the first material comprises Al203 and/or SiO2,”, as recited in Claim 20, with the remaining features.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
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/LAWRENCE C TYNES JR./Examiner, Art Unit 2899