Prosecution Insights
Last updated: October 01, 2026
Application No. 18/479,731

OPTIMIZATION OF HEATERS FOR TUNING PHOTONIC DEVICES

Non-Final OA §102
Filed
Oct 02, 2023
Examiner
PARIHAR, SUCHIN
Art Unit
Tech Center
Assignee
X Development LLC
OA Round
1 (Non-Final)
88%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
97%
With Interview

Examiner Intelligence

Grants 88% — above average
88%
Career Allowance Rate
1033 granted / 1177 resolved
+27.8% vs TC avg
Moderate +9% lift
Without
With
+8.9%
Interview Lift
resolved cases with interview
Typical timeline
2y 4m
Avg Prosecution
20 currently pending
Career history
1184
Total Applications
across all art units

Statute-Specific Performance

§101
17.4%
-22.6% vs TC avg
§103
15.5%
-24.5% vs TC avg
§102
56.2%
+16.2% vs TC avg
§112
7.9%
-32.1% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1177 resolved cases

Office Action

§102
DETAILED ACTION 1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . 2. This Non-Final office action is in response to application 18/479,731, application filed on 10/02/2023. Claims 1-20 are currently pending in this application. Information Disclosure Statement 3. The information disclosure statement (IDS) submitted on 10/02/2023, 01/02/2025 and 09/02/2025, respectively, is/are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner. Claim Rejections - 35 USC § 102 4. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention. (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. 5. Claim(s) 1-20 is/are rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as being anticipated by Parker et al. (US PG Pub No. 2022/0107542). 6. With respect to independent claim 1, Parker teaches: creating a design for an optoelectronic device (see photonic ring modulator, Abstract, para see design of photonic/opto-electronic design, para 11-15; see photonic circuit, para 15; see optically active chip/circuit region, para 11; see circuit with electro-optic effects, para 15), the actions comprising: determining, by the computing system, an initial heater design that includes one or more heater parameters (see initial tuning of heater, para 41; see heater configurations, para 4; various heater configurations, para 18; see parameters such as heater configuration, heater power, bias voltage, para 8, 16-17); determining, by the computing system, a temperature gradation by simulating performance of the initial heater design in adjusting an environmental temperature to a nominal temperature (see range of temperatures for heater power, para 16-17); simulating, by the computing system, performance of a nominal optimized design of a dispersive region of the optoelectronic device, given the temperature gradation, to determine a temperature-influenced performance loss value (see simulation/testing of tested DC voltage range/gradation of photonic/opto-electronic modulator device, para 40-45; see determining maximum loss value, para 32); determining, by the computing system, a heater parameter gradient based on the temperature-influenced performance loss value (see calibration/optimization of multiple temperatures related to loss over the range of temperatures, para 43); and revising the heater parameters based at least in part on the heater parameter gradient to create a revised heater design (see repeating calibration for multiple temperatures for determining optimal voltage bias for achieving target insertion loss over the range of temperatures, para 40-43; various heater configurations, para 18; see parameters such as heater configuration, heater power, bias voltage, para 8, 16-17). 7. With respect to claims 2 and 12, Parker teaches: wherein the actions further comprise repeating the determining the temperature gradation, simulating performance of the nominal optimized design given the temperature gradation, determining the heater parameter gradient, and revising the heater parameters based at least in part on the heater parameter gradient two or more times (see repeating calibration for multiple temperatures for determining optimal voltage bias for achieving target insertion loss over the range of temperatures, para 40-43; various heater configurations, para 18; see parameters such as heater configuration, heater power, bias voltage, para 8, 16-17). 8. With respect to claims 3 and 13, Parker teaches: wherein the heater parameters include at least one of a heater size value, a heater shape value, a heater location value, a heater timing value, and a value indicating a number of heaters (see heater placement, para 24; see examples of heaters, shape, orientation, heater reconfiguration, para 25). 9. With respect to claims 4 and 14, Parker teaches: wherein determining the heater parameter gradient based on the temperature-influenced performance loss value includes: determining, by the computing system, a loss metric based on the temperature-influenced performance loss value (see determining insertion loss, para 36); backpropagating, by the computing system, the loss metric to determine a structural gradient; and converting, by the computing system, the structural gradient to the heater parameter gradient (see feedback/back-propagation to adjust heating and achieve target loss values, para 32). 10. With respect to claims 5 and 15, Parker teaches: wherein the temperature gradation is a first temperature gradation (see simulation/testing of tested DC voltage range/gradation of photonic/opto-electronic modulator device, para 40-45; see determining maximum loss value, para 32), wherein the environmental temperature is a first environmental temperature, wherein the temperature-influenced performance loss value is a first temperature-influenced performance loss value (see determining insertion loss, para 36), and wherein the actions further comprise: determining a second temperature gradation by simulating performance of the initial heater design in adjusting a second environmental temperature to the nominal temperature (see feedback/back-propagation to adjust heating and achieve target loss values, para 32; see repeating calibration for multiple temperatures for determining optimal voltage bias for achieving target insertion loss over the range of temperatures, para 40-43; various heater configurations, para 18; see parameters such as heater configuration, heater power, bias voltage, para 8, 16-17); and simulating performance of the nominal optimized design given the second temperature gradation to determine a second temperature-influenced performance loss value (see feedback/back-propagation to adjust heating and achieve target loss values, para 32; see repeating calibration for multiple temperatures for determining optimal voltage bias for achieving target insertion loss over the range of temperatures, para 40-43; various heater configurations, para 18; see parameters such as heater configuration, heater power, bias voltage, para 8, 16-17). 11. With respect to claims 6 and 16, Parker teaches: wherein determining the loss metric based on the temperature-influenced performance loss value includes: determining a combined loss metric based on the first temperature-influenced performance loss value and the second temperature-influenced performance loss value (see initial tuning of heater, para 41; see heater configurations, para 4; various heater configurations, para 18; see parameters such as heater configuration, heater power, bias voltage, para 8, 16-17; feedback/back-propagation to adjust heating and achieve target loss values, para 32; see repeating calibration for multiple temperatures for determining optimal voltage bias for achieving target insertion loss over the range of temperatures, para 40-43; various heater configurations, para 18; see parameters such as heater configuration, heater power, bias voltage, para 8, 16-17). 12. With respect to claims 7 and 17, Parker teaches: wherein determining the loss metric includes determining a heater design loss value that represents at least one of a power consumption or an equilibrium time (see power consumption, para 15-16). 13. With respect to claims 8 and 18, Parker teaches: wherein a material specified by the heater parameters is optically absorptive (see absorption in the device, para 12-15), and wherein simulating performance of the nominal optimized design given the temperature gradation to determine the temperature-influenced performance loss value includes simulating optical properties of the initial heater design (see simulation/testing of tested DC voltage range/gradation of photonic/opto-electronic modulator device, para 40-45; see determining maximum loss value, para 32). 14. With respect to claims 9 and 19, Parker teaches: transmitting the nominal optimized design and the revised heater design to a fabrication system for fabrication (see temperature induced wavelength and nominal optimized design, para 16-17). 15. With respect to claims 10 and 20, Parker teaches: wherein the optoelectronic device is a multiplexer or a demultiplexer (see multiplexing and demultiplexing, para 34-35). Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to SUCHIN PARIHAR whose telephone number is (703)756-1970. The examiner can normally be reached on M-F 8am-5pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jack Chiang can be reached on 571-272-7483. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /SUCHIN PARIHAR/ Primary Examiner, Art Unit 2851
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Prosecution Timeline

Oct 02, 2023
Application Filed
Sep 09, 2026
Non-Final Rejection mailed — §102 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
88%
Grant Probability
97%
With Interview (+8.9%)
2y 4m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 1177 resolved cases by this examiner. Grant probability derived from career allowance rate.

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