Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Detailed Action
This office action is in response to applicant’s communication filed on 10/02/23. Claims 1-20 are pending in this application.
Information Disclosure Statement
The information disclosure statement filed on 10/02/23 has been received and is being considered.
Claim Rejections Under 35 U.S.C. §102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-20 are rejected Under 35 U.S.C. §102(a)(1)(2) as being unpatentable over Hart (US 5970372 A).
Regarding claim 1, Hart discloses an antifuse (see fig 1d, reproduced below), comprising: a substrate 108 (see fig 1d); a conductor layer in the substrate (see 102 in 108); a trench in the conductor layer (see fig 1d, disclosing angular trench in 102), the trench including a first conductor surface and a second conductor surface (see 102 having two angled surfaces); a dielectric liner in the trench (see 105 in the trench); and an electrode on the dielectric liner in the trench (see 102 and 101 on dielectric liner), the electrode comprises a first electrode surface (bottom of 101) and a second electrode surface converging to the first electrode surface (top of 102 converges with 101 at the peak of the trench, see fig 1d).
PNG
media_image1.png
304
472
media_image1.png
Greyscale
Regarding claim 2, Hart discloses the antifuse of claim 1, wherein the first electrode surface and the second electrode surface converge at a first angle of at most 90 degrees (see fig 1d disclosing a right angle of 102).
Regarding claim 3, Hart discloses the antifuse of claim 2, wherein the first electrode surface adjoins the second electrode surface at a corner (see fig 1d disclosing 101 converging with 102 at the corner of the peak, see fig 1d).
Regarding claim 4, Hart discloses the antifuse of claim 2, wherein the first conductor surface and the second conductor surface converge at a second angle substantially equal to the first angle (see angle of 101 and 102 are at right angles).
Regarding claim 5, Hart discloses the antifuse of claim 1, wherein the first electrode surface is substantially parallel to the first conductor surface (see 101 and 102) disclosing parallel electrodes.
Regarding claim 6, Hart discloses the antifuse of claim 1, wherein the electrode and the conductor layer comprise an electrically conductive material, and the electrically conductive material of the electrode is different from the electrically conductive material of the conductor layer (see 101 and 102 are separate layers).
Regarding claim 7, Hart discloses the antifuse of claim 1, wherein the electrode at least fully occupies the trench (see fig 1d, where 101 fills the trench).
Regarding claim 8, Hart discloses the antifuse of claim 1, wherein the substrate further comprises: a base substrate layer 108/110; a buried insulator layer over the base substrate layer (see 107 ); and a semiconductor layer over the buried insulator layer (see doped layer 101), wherein the conductor layer is a doped portion of the semiconductor layer.1
Regarding claim 9, Hart discloses the antifuse of claim 8, wherein a portion of the conductor layer is vertically between the trench and the buried insulator layer (see peak is between 110).
Regarding claim 10, Hart discloses the antifuse of claim 8, wherein the trench extends through the conductor layer, and the first conductor surface is spaced apart from the second conductor surface (see fig 1d, disclosing 101 and 102 is spaced apart).
Regarding claim 11, Hart discloses the antifuse of claim 10, further comprising an opening in the electrode, wherein a portion of the dielectric liner is exposed in the opening (see 105 is uncovered by 102).
Regarding claim 12, Hart discloses the antifuse of claim 11, wherein the portion of the dielectric liner is directly in contact with the buried insulator layer (see 104 in contact with 105).
Regarding claim 13, Hart discloses the antifuse of claim 8, further comprising an undoped semiconductor layer in the semiconductor layer, and the conductor layer is between the undoped semiconductor layer and the buried insulator layer (see silicon dioxide 104 on either side of 105).
Regarding claim 14, Hart discloses an antifuse (see fig 1d reproduced below), comprising: a substrate having an upper substrate surface (see fig 1b-d disclosing 103/108 having a top surface); a conductor layer in the substrate (102/105); a trench in the conductor layer (see 1d disclosing trench in 102), the trench including a first conductor surface and a second conductor surface (top 102 having angled surfaces); a dielectric liner in the trench (see liner 105); an electrode on the dielectric liner in the trench (see 101 is formed on 105), the electrode comprises a first electrode surface and a second electrode surface converging to the first electrode surface (see 105 and 102 converging at the peak of trench); and a conductive link between the conductor layer and the electrode, the conductive link extending through the dielectric liner.2
PNG
media_image1.png
304
472
media_image1.png
Greyscale
Regarding claim 15, Hart discloses the antifuse of claim 14, wherein the first electrode surface and the second electrode surface converge to a corner, and the conductive link extends from the corner (see fig 1c, disclosing two corners. convergence).
Regarding claim 16, Hart discloses the antifuse of claim 14, wherein the electrode comprises an electrically conductive material and the conductive link includes at least the electrically conductive material of the electrode (see 105 bridging 101 and 102).
Regarding claim 17, Hart discloses the antifuse of claim 14, wherein the first conductor surface and the second conductor surface adjoin the first conductor surface at a first corner(see fig 1c disclosing two corners), the first electrode surface adjoins the second electrode surface at a second corner(see fig 1c disclosing two corners), and the second corner is vertically over the first corner (see fig 1c disclosing two corners).
Regarding claim 18, Hart discloses the antifuse of claim 14, further comprising an opening in the electrode to divide the electrode into a first electrode section and a second electrode section (see 1102 does not contact 105 in a portion), and a portion of the dielectric liner is exposed in the opening(see 1102 does not contact 105 in a portion).
Regarding claim 19, Hart discloses the antifuse of claim 18, wherein each electrode section includes the first electrode surface on the dielectric liner and an end surface in the trench, wherein the end surfaces of the electrode sections are substantially vertically straight (see straight portions of 101 and 105 in fig 1c).
Regarding claim 20, Hart discloses a method of forming an antifuse (see fig 1d, reproduced below), comprising: forming a conductor layer 102 in a substrate (see conductive layer 102 formed in 108); forming a trench in the conductor layer (see notched peak formed between 101 and 102); forming a dielectric liner conformal lining the trench (see 105 formed in the trench conformally); and forming an electrode on the dielectric liner (see 101 formed on 105), the electrode comprises a first electrode surface and a second electrode surface converging to the first electrode surface (see fig 1d, disclosing 102 top and 101 bottom converging at the peak of trench, see fig 1d).
PNG
media_image1.png
304
472
media_image1.png
Greyscale
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to EDWARD CHIN whose telephone number is (571)270-1827. The examiner can normally be reached M-F 9AM-5PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Britt Hanley can be reached at (571) 270-3042. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/EDWARD CHIN/Primary Examiner, Art Unit 2893
1 See 101 and 102 may be formed of a wide variety of conductive materials, including but not limited to aluminum, copper, refractory metals such as tungsten, molybdenum, platinum, titanium including titanium-tungsten (Ti-W) and titanium nitride (Ti-N), tantalum, silicides of those metals, and arsenic-doped polysilicon. In one embodiment shown in FIG. 1A, conductive layer 101 is formed of a titanium (Ti) layer 101A, a titanium-tungsten (TiW) layer 101B and an aluminum-copper layer (AlCu) 101C. Conductive layer 102 is formed of a titanium-tungsten (TiW) layer 102A and an aluminum-copper layer (AlCu) 102B. In one embodiment, conductive layers 101 and 102 each have a thickness of between about 100-200 nm.
2 See fig 1a, and corresponding description disclosing 105 is programmed (changed to a low impedance conductive state by the application of a sufficient voltage across the layer)