DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 14, are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al., US 2016/0372497 (corresponding to US9,786,697).
In re Claim 14, Lee discloses a display apparatus (Fig. 7) comprising: a substrate SUB (Fig. 6) comprising a display area comprising pixels PXL; a first thin-film transistor TA1 comprising a first semiconductor layer (SA1, A1, DA1), and a first gate electrode G1 overlapping the first semiconductor layer (SA1, A1, DA1), with a gate-insulating layer GI1 therebetween; and a capacitor (C1, C2, C3, C4) electrically connected to the first thin-film transistor TA1, and comprising: a first electrode GC1; a second electrode GC2 overlapping the first electrode GC1 with a first inorganic insulating layer ILD2 therebetween; a third electrode GS1 overlapping the second electrode GC2 with a second inorganic insulating layer therebetween GI2; and a fourth electrode GP overlapping the third electrode GS1 with a third inorganic insulating layer (PAS, PAC) therebetween (Figs. 1-13; [0029-0176]). Lee does not explicitly indicate that the first electrode GC1 comprising a same material as the first gate electrode G1. It would have been obvious to one of ordinary skill in the art at the time the invention was made to make the first electrode GC1 comprising a same material as the first gate electrode G1 since it was known in the semiconductor art that an usage of a same material will simplify manufacturing process. (MPEP2144.I.)
In re Claim 15, Lee discloses the display apparatus of claim 14, further comprising: a first data line DL extending in a first (vertical) direction, and connected to one of a sub-pixel in an odd row or a sub-pixel in an even row; and a second data line VDD apart from the first data line DL, at a same layer as the first data line DL, extending in the first (vertical) direction, and connected to an other of the sub-pixel in the odd row and the sub-pixel in the even row (Figs. 8-12; [0140-0145]).
In re Claim 16, Lee discloses the display apparatus of claim 14, wherein the first semiconductor layer (SA1, A1, DA1) comprises a channel area A1 overlapping the first gate electrode G1, and a source area SA1 and a drain area DA1 at respective sides of the channel area A1, wherein the display apparatus further comprises an electrode S1 electrically connected to one of the source area SA1 or the drain area (Figs. 1-6), while does not specify that the third electrode GS1 of the capacitor comprises a same material as the electrode S1. It would have been obvious to one of ordinary skill in the art at the time the invention was made to make the first electrode GS1 comprising a same material as the first gate electrode S1 since it was known in the semiconductor art that an usage of a same material will simplify manufacturing process. (MPEP2144.I.)
In re Claim 17, Lee discloses the display apparatus of claim 14, further comprising a second thin-film transistor T2 comprising a second semiconductor layer A2 and a second gate electrode G2, wherein the first semiconductor layer (SA1, A1, DA1) comprises a silicon semiconductor ([0031]), and wherein the second semiconductor layer A2 comprises an oxide semiconductor ([0082]).
In re Claim 18, Lee discloses the display apparatus of claim 14, wherein the third electrode GS1 of the capacitor is electrically connected to the first electrode GC1 of the capacitor, and wherein the fourth electrode GP of the capacitor is electrically connected to the second electrode GC2 of the capacitor (Fig. 5).
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Lee as applied to claim 14 above, and further in view of Yoon et al., US 2021/0391407.
In re Claim 19, Lee discloses all limitations of Claim 19 except for a first conductive layer under the first semiconductor layer (SA1, A1, DA1), and overlapping the first semiconductor layer (SA1, A1, DA1) and the first gate electrode G1.
Yoon teaches a display device wherein a first conductive layer BML under the first semiconductor layer TFT’ (Fig, 7), and overlapping the first semiconductor layer TFT’ and the first gate electrode GE1’ (Fig, 7; [0059-0284]).
It would have been obvious to one of ordinary skill in the art at the time of the invention to combine teachings of Lee and Yoon, and to use the specified to block external light as taught by Yoon ([0072]).
Allowable Subject Matter
Claims 1-13 are allowed.
The following is an examiner’s statement of reasons for allowance:
In re Claim 1, prior-art fails to disclose a display apparatus comprising “the insulating layer being above the second inorganic insulating layer and comprising a first organic insulating layer defining an opening corresponding to the capacitor and filled with an inorganic insulating material.” Therefore, the claimed device differs from prior art devices on this point and there is no evidence it would have been obvious to make this change.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Claim 20 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Reason for indicating allowable subject matter
In re Claim 20: The prior art of record cited by the current office action, alone or in combination, fail to anticipate or render obvious such limitation of claim 20 as: “the first conductive layer is electrically connected to the second electrode and the fourth electrode of the capacitor”, in combination with limitations of Claims 14 and 19 on which it depends.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NIKOLAY K YUSHIN whose telephone number is (571)270-7885. The examiner can normally be reached Monday-Friday (7-7 PST).
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Yara B. Green can be reached at 5712703075. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/NIKOLAY K YUSHIN/Primary Examiner, Art Unit 2893