DETAILED ACTION
Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
2. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
3. Claim(s) 1-5, 10-11, 18-19, is/are rejected under 35 U.S.C. 102(a1) as being anticipated by Cheng et al., US 2018/0233572 A1.
Claim 1. Cheng et al., disclose a semiconductor device (such as the one in figs. 3, 4, 5, [0046-52]) comprising:
-a stacked structure (item 201) comprising a plurality of gate structures (items 110, 112, 114) alternately stacked with a plurality of multi-layered channel structures (items 102, 104, 106);
-wherein each multi-layered channel structure of the plurality of multi-layered channel structures comprises a stack of semiconductor layers having at least two semiconductor layers which are comprised of different semiconductor materials from each other (this limitation would read through [0004] wherein is disclosed the first gate dielectric material differs from the second gate dielectric material).
Claim 10. Cheng et al., disclose a semiconductor device (such as the one in figs. 3, 4, 5, [0046-52]) comprising:
-a nanosheet structure (item 201) comprising: a plurality of gate structures (items 110, 112, 114);
-and a plurality of multi-layered channel structures (items 102, 104, 106) alternately stacked with the plurality of gate structures;
-wherein each multi-layered channel structure of the plurality of multi- layered channel structures comprises a stack of semiconductor layers comprising a second semiconductor layer disposed between a first semiconductor layer and a third semiconductor layer (this limitation would read through fig. 5, (items 102, 104, 106);
-and wherein the first and third semiconductor layers comprise a first semiconductor material and the second semiconductor layer comprises a second semiconductor material different from the first semiconductor material (this limitation would read through [0004] wherein is disclosed the first gate dielectric material differs from the second gate dielectric material).
Claim 18. Cheng et al., disclose a semiconductor device (such as the one in figs. 3, 4, 5, [0046-52]) comprising:
-a nanosheet transistor (item 201) comprising a plurality of multi-layered channel structures (items 102, 104, 106) in a stacked configuration with a plurality of gate structures (items 110, 112, 114);
-wherein each multi-layered channel structure of the plurality of multi-layered channel structures comprises a stack of semiconductor layers comprising a middle semiconductor layer disposed between two outer semiconductor layers;
-and wherein the two outer semiconductor layers comprise a different semiconductor material than a semiconductor material of the middle semiconductor layer (this limitation would read through [0004] wherein is disclosed the first gate dielectric material differs from the second gate dielectric material).
Claims 2-5. Cheng et al., disclose the semiconductor device of claim 1, wherein the stack of semiconductor layers of each multi-layered channel structure comprises a first semiconductor layer, a second semiconductor layer stacked on the first semiconductor layer and a third semiconductor layer stacked on the second semiconductor layer (this limitation would read through [0035] wherein is disclosed for example, forming the GAA nanosheets from alternating layers of channel nanosheets formed from a first type of semiconductor material (e.g., Si for n-type FETs, and SiGe for p-type FETs) and sacrificial nanosheets formed from a second type of semiconductor material (e.g., SiGe for n-type FETs, and Si for p-type FETs).
Claims 11, 19. Cheng et al., disclose the semiconductor device of claim 10, wherein: the first semiconductor material comprises silicon germanium; and the second semiconductor material comprises silicon (this limitation would read through [0035] wherein is disclosed for example, forming the GAA nanosheets from alternating layers of channel nanosheets formed from a first type of semiconductor material (e.g., Si for n-type FETs, and SiGe for p-type FETs) and sacrificial nanosheets formed from a second type of semiconductor material (e.g., SiGe for n-type FETs, and Si for p-type FETs).
Allowable Subject Matter
4. Claims 6-9, 12-17, 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
(A) Claim 6 contains allowable subject matter because none of references of record teach or suggest, either singularly or in combination, at least the limitation of wherein parts of the first, second and third semiconductor layers are disposed between a plurality of spacers, wherein respective ones of the plurality of spacers are disposed adjacent respective ones of the plurality of gate structures.
(B) Claim 7 contains allowable subject matter because none of references of record teach or suggest, either singularly or in combination, at least the limitation of further comprising a plurality of additional semiconductor layers respectively disposed on respective sides of respective ones of the plurality of multi-layered channel structures, wherein respective ones of the plurality of additional semiconductor layers are disposed on side surfaces of the first, second and third semiconductor layers.
(C) Claims 8-9, are also allowable subject matter as depend on claim 7.
(D) Claim 12 contains allowable subject matter because none of references of record teach or suggest, either singularly or in combination, at least the limitation of wherein: the nanosheet structure further comprises a plurality of spacers disposed on sides of the plurality of gate structures; and parts of the first, second and third semiconductor layers are disposed between two of the plurality of spacers.
(E) Claim 13 contains allowable subject matter because none of references of record teach or suggest, either singularly or in combination, at least the limitation of wherein the nanosheet structure further comprises a plurality of spacers disposed on sides of the plurality of gate structures at least one of over and under portions of respective ones of the plurality of multi-layered channel structures.
(F) Claim 14, is/are also allowable subject matter as depend on claim 13.
(G) Claim 15 contains allowable subject matter because none of references of record teach or suggest, either singularly or in combination, at least the limitation of further comprising a plurality of additional semiconductor layers respectively disposed on respective sides of respective ones of the plurality of multi-layered channel structures, wherein respective ones of the plurality of additional semiconductor layers are disposed on side surfaces of the first, second and third semiconductor layers.
(H) Claims 16-17, are also allowable subject matter as depend on claim 15.
(I) Claim 20 contains allowable subject matter because none of references of record teach or suggest, either singularly or in combination, at least the limitation of wherein: the nanosheet transistor further comprises a plurality of spacers disposed on sides of the plurality of gate structures; and end portions of the two outer semiconductor layers and of the middle semiconductor layer are disposed between two of the plurality of spacers.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to WILNER JEAN BAPTISTE whose telephone number is (571)270-7394. The examiner can normally be reached M-T 8:00-6:00.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Dale Page can be reached at 571-270-7877. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/W.J/Examiner, Art Unit 2899 /DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899
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