DETAILED ACTION
Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Un-der 37 CFR 1.114
2. A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 08/10/2026 has been entered.
Claim Rejections - 35 USC § 102
3. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
4. Claim(s) 1 is/are rejected under 35 U.S.C. 102(a1) as being anticipated by Frougier et al., US-20190058052-A1.
Claim 1. Frougier et al., disclose a semiconductor device (such as the one in fig. 9) comprising:
-a transistor (as item 50, a Fin-FET, [0033]) comprising:
-a stacked structure comprising a plurality of gate structures (item 48, fig. 9) alternately stacked with a plurality of multi-layered channel structures (item 10),
-and a first source/drain region (items 36/44, on the left) and a second source/drain region (items 48/36 on the right) disposed on opposite sides of the stacked structure and coupled to respective ends of each multi-layered channel structure of the plurality of multi-layered channel structures (as seen in the structure of fig. 9),
-wherein each multi-layered channel structure of the plurality of multi-layered channel structures comprises a stack of semiconductor layers having at least two semiconductor layers which are disposed in contact with each other and comprised of different semiconductor materials from each other (this limitation would read through [0012], wherein is disclosed the semiconductor layers 11 may be composed of silicon (Si), and the semiconductor layers 13 may be composed of silicon germanium (Si-Ge)).
Allowable Subject Matter
5. Claims 2-9 are objected to as being dependent upon a rejected base claim but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
(A) Claim 2, contains allowable subject matter because none of references of record teach or suggest, either singularly or in combination, at least the limitation of wherein the stack of semiconductor layers of each multi-layered channel structure comprises a first semiconductor layer, a second semiconductor layer stacked on the first semiconductor layer and a third semiconductor layer stacked on the second semiconductor layer.
(B) Claims 3-9 are also allowable subject matter, as depend on claim 2.
6. Claims 10-20 are allowed.
Reasons for Allowance
7. The following is an examiner's statement of reasons for allowance:
8. Regarding claims 10-17, the prior art failed to disclose or reasonably suggest a plurality of gate structures; a plurality of multi-layered channel structures alternately stacked with the plurality of gate structures; and a first source/drain region and a second source/drain region coupled to respective ends of each multi-layered channel structure of the plurality of multi-layered channel structures; wherein each multi-layered channel structure of the plurality of multi-layered channel structures comprises a stack of semiconductor layers comprising a second semiconductor layer disposed between and in contact with a first semiconductor layer and a third semiconductor layer; and wherein the first and third semiconductor layers comprise a first semiconductor material and the second semiconductor layer comprises a second semiconductor material different from the first semiconductor material.
9. Regarding claims 18-20, the prior art failed to disclose or reasonably suggest a nanosheet transistor comprising a plurality of multi-layered channel structures in a stacked configuration with a plurality of gate structures; wherein each multi-layered channel structure of the plurality of multi-layered channel structures comprises a stack of semiconductor layers comprising a middle semiconductor layer disposed between and in contact with two outer semiconductor layers; and wherein the two outer semiconductor layers comprise a different semiconductor material than a semiconductor material of the middle semiconductor layer.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to WILNER JEAN BAPTISTE whose telephone number is (571)270-7394. The examiner can normally be reached M-T 8:00-6:00.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Dale Page can be reached at 571-270-7877. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/W.J/Examiner, Art Unit 2899 /DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899
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