DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant election of group I, Claims 1-7, without traverse, is acknowledged. Claims 8-16 are withdrawn from consideration.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Blank (US 2017/0338338), (hereinafter, Blank).
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RE Claim 1, Blank discloses in FIGS. 1-6 a semiconductor device and a method of making the same. Blank discloses a semiconductor device, comprising:
a semiconductor substrate 101 having a first major surface, referring to FIG. 2R;
one or more trenches 120 formed in the first major surface and having a base and a side wall extending from the base to the first major surface, referring to FIG. 2C;
an anchoring layer 128 “plug”. Examiner notes that the 128 “plug” layer formed by of tungsten or titanium nitride is functionally equivalent to an anchoring layer since it is connected to the conductive member 122 while the conductive member 122 is surrounded by the cavity 126 such that layer 128 is anchored with the semiconductor substrate 101, hence meeting the claimed limitation;
a conductive member 122 “filling structure that fills the trench 120”, made of polysilicon [0025, 0048 and 0048] arranged in the one or more trenches 120 and spaced apart from the side wall of the one or more trenches 120 by a cavity 126 formed in the one or more trenches 120, referring to FIGS. 3A-3C [0028-0030, 0034 and 0072],
wherein the anchoring layer 128 extends from the first major surface of the semiconductor substrate 101/113 over the cavity 126 and onto an upper surface of the conductive member 120.
RE Claim 2, Blank discloses a semiconductor device, wherein the anchoring layer 128 comprises at least one opening 129, referring to FIG. 3B that is positioned above the cavity 126 and the semiconductor device further comprises a sealing layer 127 that is arranged on the anchoring layer 128 and covers the at least one opening to seal the cavity 126, referring to FIG. 3C.
RE Claim 3, Blank discloses a semiconductor device, further comprising an interface layer 116 arranged on the first major surface of the semiconductor substrate 101/113 and that leaves the one or more trenches 120 uncovered, referring to FIG. 3C.
RE Claim 4, Blank discloses a semiconductor device, wherein the interface layer 116 is spaced apart from the sidewall of the one or more trenches 120 by a portion of the first major surface of the semiconductor substrate 101/113, referring to FIG. 3C. Since the interface layer 116 does not overlap the sidewall of the trench 120, the claimed limitation is met, and
wherein the anchoring layer 128 is in direct contact with the portion of the first major surface of the semiconductor substrate 101/113, referring to Fig. 2R.
RE Claim 5, Blank discloses a semiconductor device, wherein the anchoring layer comprises a material with a Young's modulus of at least 200 GPa. Since the anchoring layer 128 is made from titanium nitride, which has Young's modulus value of 200 -600GPa or tungsten, which has Young's modulus value of 240 -480GPa. Therefore, the claimed limitation is met.
RE Claim 6, Blank discloses a semiconductor device, wherein each one of the one or more trenches 120 is an elongate trench or a columnar trench, referring to FIGS. 1-6.
RE Claim 7, Blank discloses a semiconductor device, wherein the semiconductor substrate 101/113 comprises a first conductivity type “n-type” and a plurality of transistor cells, due to the presence of plurality of sources and a common drain the transistor cells limitation is met [0038, 0062 and 0063] each transistor cell comprising a drain region 113 of the first conductivity type “n-type”, a drift region 112 of the first conductivity type “n-type” on the drain region 113 [0038], referring to FIG. 2A, a body region 114a of a second conductivity type “p-type” that opposes the first conductivity on the drift region 112 [0061], a source region 114b of the first conductivity type “n-type” on the body region 114a, a gate electrode 132, referring to FIG. 2K, and the one or more trenches 120 with the conductive member 122, and wherein the conductive member 122 provides a field plate “field electrode needle” [0041].
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. In the instant case, Haase et al. (US 2017/0330943) disclose a power semiconductor device includes a semiconductor substrate having a drift region, a gate electrode trench in the semiconductor substrate and a field electrode needle trench in the semiconductor substrate. The gate electrode trench extends into the drift region and includes a gate electrode. The gate electrode is arranged in the gate electrode trench and electrically insulated from the drift region by a gate dielectric layer arranged between the gate electrode and the drift region. The field electrode needle trench is laterally spaced from the gate electrode trench and extends into the drift region. The field electrode needle trench includes a field electrode arranged in the field electrode needle trench and electrically insulated from the drift region by a cavity formed between the field electrode and the drift region.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to YASSER ABDELAZIEZ whose telephone number is (571)270-5783. The examiner can normally be reached Monday - Friday 9 am - 6 pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Leonard Chang can be reached at (571)270-3691. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/YASSER A ABDELAZIEZ, PhD/Primary Examiner, Art Unit 2898
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