DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Blank (US 2017/0338338), (hereinafter, Blank).
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RE Claim 1, Blank discloses in FIGS. 1-6 a semiconductor device and a method of making the same. Blank discloses a semiconductor device, comprising:
a semiconductor substrate 101 having a first major surface 101a, referring to FIG. 1A;
one or more trenches 120 formed in the first major surface and having a base and a side wall extending from the base to the first major surface 101a, referring to FIG. 1A;
an anchoring layer 194 “nitride”/”196, referring to FIGS. 1I-1K. Examiner notes that the layer 194 “nitride” formed of nitride material is functionally anchored to the conductive pillar 122, hence meeting the claimed limitation;
a conductive member 122 “filling structure that fills the trench 120, made of polysilicon [0025, 0048 and 0048] arranged in the one or more trenches 120 and spaced apart from the side wall of the one or more trenches 120 by a cavity 126 formed in the one or more trenches 120, referring to FIGS. 1G-1K [0025],
wherein the anchoring layer 128 extends from a portion of the first major surface 101a of the semiconductor substrate 101 over the cavity 126 and onto an upper surface of the conductive member 122, referring to FIGS. 1J-1K.
RE Claim 2, Blank discloses a semiconductor device, wherein the anchoring layer 194 comprises at least one opening 129, referring to FIG. 1J that is positioned above the cavity 126 and the semiconductor device further comprises a sealing layer 196 “oxide” that is arranged on the anchoring layer 194 and covers the at least one opening 129 to seal the cavity 126, referring to FIG. 1K.
RE Claim 5, Blank discloses a semiconductor device, wherein the anchoring layer comprises a material with a Young's modulus of at least 200 GPa. Since the anchoring layer 194 is made from nitride, which has Young's modulus value of 250 -600GPa, depending on the alloy within the nitride alloy. Therefore, the claimed limitation is met.
RE Claim 6, Blank discloses a semiconductor device, wherein each one of the one or more trenches 120 is an elongate trench or a columnar trench, referring to FIGS. 1-6.
RE Claim 17, Blank discloses a semiconductor device, wherein the anchoring layer 194 extends over an entire open end 129 of the one or more trenches 120, referring to FIG. 1.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or non-obviousness.
Claim(s) 3 and 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Blank (US 2017/0338338), (hereinafter, Blank).
RE Claim 3, Blank does not disclose a semiconductor device in embodiment of FIGS. 1A-1K, further comprising an interface layer arranged on the first major surface of the semiconductor substrate and that leaves the one or more trenches uncovered.
However, Blank discloses a semiconductor device in embodiment of FIGS. 2-3 a similar semiconductor device shown in the embodiment of FIG. 1, further comprising a multi-layered dielectric layer 116, comprising first, second and third dielectric layers [0065], one of which is equivalent to an interface layer arranged on the first major surface of the semiconductor substrate 101/113 and that leaves the one or more trenches 120 uncovered, referring to FIGS. 2P and 3C.
Therefore, it would have been obvious for one of ordinary skill in the art prior to the effective filing date of the instant application to utilize the interface layer of the embodiment of FIGS. 2 and 3 of Blank’s disclosure in the first disclosed embodiment of FIG. 1 of Blank’s disclosure in order to achieve better substrate major surface passivation.
RE Claim 7, Blank does not disclose a semiconductor device in embodiment of FIGS. 1A-1K, wherein the semiconductor substrate comprises a first conductivity and a plurality of transistor cells, , a drift region of the first conductivity type on the drain region, a body region 114a of a second conductivity type that opposes the first conductivity on the drift region, a source region of the first conductivity type on the body region, a gate electrode, and the one or more trenches with the conductive member, and wherein the conductive member provides a field plate.
However, Blank discloses, in the embodiments of FIGS. 2 and 3 a semiconductor device in embodiment of FIGS. 1A-1K, wherein the semiconductor substrate 101/113 comprises a first conductivity type “n-type” and a plurality of transistor cells, due to the presence of plurality of sources and a common drain the transistor cells limitation is met [0038, 0062 and 0063] each transistor cell comprising a drain region 113 of the first conductivity type “n-type”, a drift region 112 of the first conductivity type “n-type” on the drain region 113 [0038], referring to FIG. 2A, a body region 114a of a second conductivity type “p-type” that opposes the first conductivity on the drift region 112 [0061], a source region 114b of the first conductivity type “n-type” on the body region 114a, a gate electrode 132, referring to FIG. 2K, and the one or more trenches 120 with the conductive member 122, and wherein the conductive member 122 provides a field plate “field electrode needle” [0041].
Therefore, it would have been obvious for one of ordinary skill in the art prior to the effective filing date of the instant application to utilize the transistor array structure of the embodiment of FIGS. 2 and 3 of Blank’s disclosure in the first disclosed embodiment of FIG. 1 of Blank’s disclosure in order to achieve an integrated power device.
Allowable Subject Matter
Claims 4 and 18 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Response to Arguments
Applicant's arguments filed 07/09/2026 have been fully considered but they are not persuasive. In the instant case, the embodiments of FIGS. 1-6 of Blank are obvious variant of the disclosed invention of FIG. 1, as demonstrated in the above rejection, hence the rejection is maintained.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. In the instant case, SHIRAKAWA et al. (US 2019/0140084) disclose an edge termination region, in a carrier drawing region between an active region and a gate runner part, a p-type contact region is provided in a surface region of a p-type well region. In the carrier drawing region, in second contact holes formed an interlayer insulating film, a contact plug is embedded in each via the barrier metal, and contacts of the p-type contact region and the barrier metal at an emitter electric potential are formed. The contacts of the carrier drawing region are disposed in a striped layout extending along an outer periphery of the active region; the contacts surround the active region. A contact resistance of the contacts of the carrier drawing region is higher than a contact resistance of a contact (emitter contact) of a MOS gate.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to YASSER ABDELAZIEZ whose telephone number is (571)270-5783. The examiner can normally be reached Monday - Friday 9 am - 6 pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Leonard Chang can be reached at (571)270-3691. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/YASSER A ABDELAZIEZ, PhD/Primary Examiner, Art Unit 2898
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