Prosecution Insights
Last updated: April 19, 2026
Application No. 18/480,254

SEMICONDUCTOR DEVICE

Non-Final OA §102§103§112
Filed
Oct 03, 2023
Examiner
ABDELAZIEZ, YASSER A
Art Unit
2898
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Mitsubishi Electric Corporation
OA Round
1 (Non-Final)
86%
Grant Probability
Favorable
1-2
OA Rounds
2y 3m
To Grant
89%
With Interview

Examiner Intelligence

Grants 86% — above average
86%
Career Allow Rate
687 granted / 798 resolved
+18.1% vs TC avg
Minimal +3% lift
Without
With
+3.3%
Interview Lift
resolved cases with interview
Typical timeline
2y 3m
Avg Prosecution
34 currently pending
Career history
832
Total Applications
across all art units

Statute-Specific Performance

§101
1.6%
-38.4% vs TC avg
§103
46.5%
+6.5% vs TC avg
§102
30.4%
-9.6% vs TC avg
§112
18.5%
-21.5% vs TC avg
Black line = Tech Center average estimate • Based on career data from 798 resolved cases

Office Action

§102 §103 §112
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claims 1-6 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. The term “close contact with the sealing material” in claims 1-5 is a relative term which renders the claim indefinite. The term “contact” is not defined by the claim, the specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention. In the instant case, the lid and other surfaces claimed appear to be in direct contact with the sealing material, while close contact can broadly mean “nearby” and not necessarily direct contact, contrary to the disclosed invention. Examiner will consider direct contact and a proximal distance spaced apart from the seal material either scenario will read on the claimed limitation. Examiner asserts the broadest reasonable interpretation of the claims in light of the specification without importing limitation from the disclosed invention, which is impermissible. Applicant clarification is required. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 1, 2, 5 and 6 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by ISHIBASHI et al. (US 2019/0103330), (hereinafter, ISHIBASHI). PNG media_image1.png 603 1050 media_image1.png Greyscale RE Claim 1, ISHIBASHI discloses in FIGS. 1-9 a semiconductor device includes an insulating substrate, a semiconductor element provided on the insulating substrate, a case frame, a press-fit terminal, and a sealing member provided on an inner side of an inner wall part on the insulating substrate to seal the semiconductor element. ISHIBASHI discloses a semiconductor device, referring to FIGS. 5, 6 and 8 shown above, comprising: a semiconductor chip 9 “semiconductor element” [0019, 0021, 0023 and 0030], referring to FIGS. 6 and 8; a case 2/102 “case frame”, referring to FIGS. 6 and 8 [0022, 0024-0026]; a sealing material 11 arranged in the case and sealing the semiconductor chip 9, referring to FIGS. 6 and 8; and a lid 30 “PCB” in close contact with the sealing material 30. First examiner considers the PCB is functionally equivalent to a “lid”, hence meeting the claimed limitation. Furthermore, it is clear in FIG. 8 that the upper surface 11a of the sealing resin “member” is flush with the upper ends of the inner wall parts 12 [0033], which have the upper sealing resin surface 11a is in close proximity to lower surface of the PCB “lid” 30, hence meeting the claimed limitation of “a lid 30 “PCB” in close contact with the sealing material 30”, hence meeting the claimed limitation, wherein the case has at least one projection 20 “press-fit terminal”/120 “external electrode terminal”, referring to FIGS. 5, 6 and 8, the lid 30 “PCB” is provided with at least one first hole 30a “through hole”, and the at least one projection 20 is in the at least one first hole 30a, referring to FIGS. 6 and 8, respectively, whereby the lid 30 “PCB” is fixed to the case 2/102, referring to FIG. 8. RE Claim 2, ISHIBASHI discloses a semiconductor device, wherein the at least one first hole 30a is provided on a surface of the lid 30 “PCB” that is in close contact with the sealing material 11. It is clear in FIG. 8 that the upper surface 11a of the sealing resin “member” is flush with the upper ends of the inner wall parts 12 [0033], which have the upper sealing resin surface 11a is in close proximity to lower surface of the PCB “lid” 30, hence meeting the claimed limitation of “a lid 30 “PCB” in close contact with the sealing material 30”, hence meeting the claimed limitation. RE Claim 5, ISHIBASHI discloses a semiconductor device, wherein a second hole 30a extending from a surface in close contact with the sealing material to a surface opposite to the surface in close contact with the sealing material is provided at an end portion of the lid in plan view, referring to FIGS. 6 and 8. It is clear in FIG. 8 that the upper surface 11a of the sealing resin “member” is flush with the upper ends of the inner wall parts 12 [0033], which have the upper sealing resin surface 11a is in close proximity to lower surface of the PCB “lid” 30, hence meeting the claimed limitation of “a lid 30 “PCB” in close contact with the sealing material 30”, hence meeting the claimed limitation. RE Claim 6, ISHIBASHI discloses a semiconductor device, wherein the at least one projection 20 is a plurality of projections, referring to FIGS. 1, 2, 6 and 8, an inner side surface of the case has a plurality of surfaces separated by sides, and each of the plurality of surfaces is provided with any of the plurality of projections 20, referring to FIG. 1. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or non-obviousness. Claim(s) 3 and 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over ISHIBASHI et al. (US 2019/0103330), (hereinafter, ISHIBASHI) in view of Yang et al. (US 2021/0384099), (hereinafter, Yang). RE Claim 3, ISHIBASHI does not disclose a semiconductor device, wherein the surface of the lid 30 “PCB” in close contact with the sealing material is convex toward the sealing material. However, in a related art, Yang discloses a packaged semiconductor device with a heat-generating component positioned on a surface of the substrate, an enclosure at least partially surrounding the substrate and the heat-generating component, and a thermal interface material disposed between the heat-generating component and the enclosure, wherein an enclosure cover 212 with pedestals 516a, 516b, 516c, that are partially non-planar with in close “direct” contact with a thermal interface material 514a,514b,514c, is convex toward the thermal interface material. Therefore, it would have been obvious for one of ordinary skill in the art at the effective filing date of the instant application have pedestal with the same shape of Yang as part of the lid “PCB” 30 of in close “direct” contact of the seal material layer 11 of ISHIBASHI disclosure, a well-known design choice, in order to achieve better thermal dissipation. RE Claim 4, ISHIBASHI does not disclose a semiconductor device, wherein Yang discloses a packaged semiconductor device with a heat-generating component positioned on a surface of the substrate, an enclosure at least partially surrounding the substrate and the heat-generating component, and a thermal interface material disposed between the heat-generating component and the enclosure, wherein the surface of the lid 212 with pedestals 516a, 516b, 516c, that are partially non-planar with in close contact with the thermal interface material 514a,514b,514c, that is a smooth curved surface between a point located closest toward the thermal interface material side and an outer circumference of the surface of the lid 212 in close contact with the thermal interface material. Therefore, it would have been obvious for one of ordinary skill in the art at the effective filing date of the instant application have pedestal with the same shape of Yang as part of the lid “PCB” 30 of in close “direct” contact of the seal material layer 11 of ISHIBASHI disclosure, a well-known design choice, in order to achieve better thermal dissipation. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to YASSER ABDELAZIEZ whose telephone number is (571)270-5783. The examiner can normally be reached Monday - Friday 9 am - 6 pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Leonard Chang can be reached at (571)270-3691. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /YASSER A ABDELAZIEZ, PhD/Primary Examiner, Art Unit 2898
Read full office action

Prosecution Timeline

Oct 03, 2023
Application Filed
Jan 15, 2026
Non-Final Rejection — §102, §103, §112
Apr 01, 2026
Interview Requested
Apr 07, 2026
Examiner Interview Summary
Apr 07, 2026
Applicant Interview (Telephonic)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12595167
DUAL MICRO-ELECTRO MECHANICAL SYSTEM AND MANUFACTURING METHOD THEREOF
2y 5m to grant Granted Apr 07, 2026
Patent 12588551
SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR PACKAGE
2y 5m to grant Granted Mar 24, 2026
Patent 12588193
SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME
2y 5m to grant Granted Mar 24, 2026
Patent 12581641
MEMORY CELL, MEMORY AND METHOD FOR MANUFACTURING MEMORY
2y 5m to grant Granted Mar 17, 2026
Patent 12575199
IMAGE SENSOR DEVICES INCLUDING A SUPERLATTICE
2y 5m to grant Granted Mar 10, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

AI Strategy Recommendation

Get an AI-powered prosecution strategy using examiner precedents, rejection analysis, and claim mapping.
Powered by AI — typically takes 5-10 seconds

Prosecution Projections

1-2
Expected OA Rounds
86%
Grant Probability
89%
With Interview (+3.3%)
2y 3m
Median Time to Grant
Low
PTA Risk
Based on 798 resolved cases by this examiner. Grant probability derived from career allow rate.

Sign in with your work email

Enter your email to receive a magic link. No password needed.

Personal email addresses (Gmail, Yahoo, etc.) are not accepted.

Free tier: 3 strategy analyses per month