DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 2, 5-10, 14 and 15 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by MURAKAMI et al. (US 2017/0301603), (hereinafter, MURAKAMI).
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RE Claim 1, MURAKAMI discloses in FIGS. 1-14 a semiconductor module for power control of a power semiconductor device and a method of making the same. MURAKAMI discloses a semiconductor device comprising:
a semiconductor chip 5;
a case 3;
a sealing material 36 “heat dissipating resin” arranged in the case 3 and sealing the semiconductor chip 5; and
a lid 9 “control circuit board” in direct contact with the sealing material 35, referring to FIG. 1, wherein the case 3 has at least one projection 33 “control signal terminal”, the lid 9 “control circuit board” is provided with at least one first hole, and the at least one projection 33 is in the at least one first hole, respectively, whereby the lid is fixed to the case 3. Examiner notes that the projection 33 “control signal terminal” [0047]. Since the projection 33 “control signal terminal” is passing through the lid 9 “control circuit board”, hence passing through an opening, hence the limitation of “one first hole” is met.
RE Claim 2, MURAKAMI discloses a semiconductor device, wherein the at least one first hole, through which the projection 33 “control signal terminal” is passing, is provided on a surface of the lid 9 “control circuit board”, referring to Claim 1 rejection, that is in direct contact with the sealing material 36 “heat dissipating resin”, referring to FIG. 1.
RE Claim 5, MURAKAMI discloses a semiconductor device, wherein a second hole extending from a surface in direct contact with the sealing material 36 “heat dissipating resin” to a surface of the lid 9 “control circuit board” opposite to the surface in direct contact with the sealing material 36 “heat dissipating resin” is provided at an end portion of the lid 9 “control circuit board” in plan view. Examiner asserts that the limitation is met since a control signal terminal 32 is passing through an end portion of the lid 9 “control circuit board”.
RE Claim 6, MURAKAMI discloses a semiconductor device, wherein the at least one projection is a plurality of projections 15, an inner side surface of the case 3 has a plurality of surfaces separated by sides, and each of the plurality of surfaces is provided with any of the plurality of projections 15 [0042], referring to FIG. 2.
RE Claim 7, MURAKAMI discloses a semiconductor device, wherein the at least one projection 15 projects from an inner side surface of the case 3, referring to FIG. 2.
RE Claim 8, MURAKAMI discloses a semiconductor device, wherein a portion of the projection 33 between the lid 9 “control circuit board” and the inner side surface of the case is surrounded by the sealing material 36 “heat dissipating resin”.
RE Claim 9, MURAKAMI discloses a semiconductor device, wherein the at least one first hole includes a first surface facing upward and the at least one projection includes a second surface facing downward toward the first surface, respectively. Since the projection 33 is passing through the lid 9, i.e. passing through a hole made to pass through the lid 9 “control circuit board”, it is inherent for the first hole to have a first surface facing upward and the at least one projection includes a second surface facing downward toward the first surface, respectively, hence meeting the claimed limitation.
RE Claim 10, MURAKAMI discloses a semiconductor device, wherein the first surface is in direct contact with the second surface, referring to FIG. 1.
RE Claim 13, MURAKAMI discloses a semiconductor device, wherein the at least one projection is a plurality of projections 15, the plurality of projections 15 project from an inner side surface of the case.
RE Claim 14, MURAKAMI discloses a semiconductor device, wherein the at least one projection 33 is a plurality of projections 15, the at least one first hole is a plurality of first holes, the plurality of first holes each include a first surface facing upward and the plurality of projections each include a second surface facing downward toward a respective one of the first surfaces, referring to FIG. 2.
RE Claim 15, MURAKAMI discloses a semiconductor device, wherein each of the first surfaces is in direct contact with a corresponding one of the second surfaces.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or non-obviousness.
Claim(s) 3 and 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over MURAKAMI et al. (US 2017/0301603), (hereinafter, MURAKAMI) in view of Yang et al. (US 2021/0384099), (hereinafter, Yang).
RE Claim 3, MURAKAMI does not disclose a semiconductor device, wherein
the surface of the lid 30 “PCB” in close contact with the sealing material is convex toward the sealing material.
However, in a related art, Yang discloses a packaged semiconductor device with a heat-generating component positioned on a surface of the substrate, an enclosure at least partially surrounding the substrate and the heat-generating component, and a thermal interface material disposed between the heat-generating component and the enclosure, wherein an enclosure cover 212 with pedestals 516a, 516b, 516c, that are partially non-planar with in close “direct” contact with a thermal interface material 514a,514b,514c, is convex toward the thermal interface material.
Therefore, it would have been obvious for one of ordinary skill in the art at the effective filing date of the instant application have pedestal with the same shape of Yang as part of the lid “PCB” 9 of in close “direct” contact of the seal material layer 36 of MURAKAMI disclosure, a well-known design choice, in order to achieve better thermal dissipation.
RE Claim 4, MURAKAMI does not disclose a semiconductor device, wherein
Yang discloses a packaged semiconductor device with a heat-generating component positioned on a surface of the substrate, an enclosure at least partially surrounding the substrate and the heat-generating component, and a thermal interface material disposed between the heat-generating component and the enclosure, wherein the surface of the lid 212 with pedestals 516a, 516b, 516c, that are partially non-planar with in close contact with the thermal interface material 514a,514b,514c, that is a smooth curved surface between a point located closest toward the thermal interface material side and an outer circumference of the surface of the lid 212 in close contact with the thermal interface material.
Therefore, it would have been obvious for one of ordinary skill in the art at the effective filing date of the instant application have pedestal with the same shape of Yang as part of the lid “PCB” 9 of in close “direct” contact of the seal material layer 36 of MURAKAMI disclosure, a well-known design choice, in order to achieve better thermal dissipation.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Allowable Subject Matter
Claims 11, 12, 16 and 17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. In the instant case, Kim et al. (US 2014/0167242) disclose a power module package including: a first module configured of a first substrate having one surface and the other surface, a first semiconductor chip mounted on one surface of the first substrate, and a first sealing member formed to cover the first semiconductor chip mounted on one surface of the first substrate from both sides in a thickness direction of the first substrate and expose the other surface of the first substrate; and a case enclosing the first module.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to YASSER ABDELAZIEZ whose telephone number is (571)270-5783. The examiner can normally be reached Monday - Friday 9 am - 6 pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Leonard Chang can be reached at (571)270-3691. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/YASSER A ABDELAZIEZ, PhD/Primary Examiner, Art Unit 2898
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