DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Acknowledgement of Amendment
Applicant amendment filed 05/04/26 has been acknowledged.
Applicant amended a few paragraphs of the specification and Claims 1, 2, 17; Applicant further added new Claims 18-20.
Status of Claims
Claims 1-20 are examined on merits herein.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-8, 11-14, and 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over Ito (US 2019/0043827) in view of Watanabe et al. (JP 2000349207).
In re Claim 1, Ito teaches a semiconductor device comprising (Fig. 9 and Annotated Fig. 9):
Annotated Fig. 9
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a semiconductor element 2 (paragraph 0029) that includes an element body (between electrodes 21 and 22) containing a semiconductor (paragraph 0033), and a first electrode 22 (paragraph 0036) disposed on the element body;
a first wire 3 (paragraph 0029) joined to the first electrode 22;
a sealing resin 5 (paragraph 0029) that covers the semiconductor element 2 and the first wire 3, and
a covering portion 4 (paragraph 0029) interposed between the first electrode 22 and the sealing resin 5, wherein
the first wire 3 includes a first portion (First portion in Annotated Fig. 9, e.g., a portion of the first wire between dotted lines) that extends from a location overlapping with the first electrode 22 and to over an edge of the first electrode 22 as viewed in a thickness direction of the semiconductor element,
the covering portion 4 contains a material (such as a resin with a metal filler or a metallic material such as tin alloy, paragraph 0045) having a higher elastic modulus than the sealing resin 5 (which is made from silicone gel, paragraph 0048), and the covering portion 4 is in contact with the first portion of the first wire 3.
Ito does not state that the covering portion 4 has a thermal conductivity higher than that of the sealing resin 5, Ito teaches only ratios of elastic modulus of these materials. However, there are arts (see, for example, Rabst, NPL, paragraph 2.3) teaching that a thermal conductivity of a material is proportional to elastic modulus of this material. Accordingly, it would have been inherent (and/or obvious) for the Ito device that the covering portion has a higher thermal conductivity than that of the sealing reason.
Please, be advised that it is also known in the art that when a stack of two materials covers a heat generating element, a material with a higher thermal conductivity shall be disposed closer to the heat generating element than another material of the stack, in order to increase heat dissipation from this element: see Fig. 1 and paragraph 0072 of Ishimaru, US 2005/0045369, on this common knowledge in the art.
Ito does not teach that an entirety of the first portion is parallel to a plane orthogonal to the thickness direction.
Watanabe teaches a first wire 14 (Fig. 1, page 4, underlined section) joined to a first electrode 12 and including a first portion (a horizontal part of 14) that extends from a location overlapping with the first electrode 12 and to over an edge of the first electrode, wherein an entirety of the first portion is parallel to a plane orthogonal to a thickness direction of chip 1.
Ito and Watanabe teach analogous arts directed to a wire bonded to an electrode of a chip, and one of ordinary skill in the art before the effective date of filing the application would have had a reasonable expectation of success in modifying the Ito device in view of the Watanabe device, since they are from the same field of endeavor, and Watanabe created a successfully operated device.
It would have been obvious for one of ordinary skill in the art before the effective date of filing the application to modify the Ito first wire by creating it in such shape that the entirety of its first portion (FP, as is shown below) would be parallel to a plane orthogonal to the thickness direction, as presented in Annotated Modified Fig. 9 (e.g., by having a shape similar to a portion of wire 14 of Watanabe, but with a vertical portion directed “up” - for connection with a remaining portion of the Ito’ wire 3), if such shape of the first wire is preferred for the manufacturer.
Annotated Modified Fig. 1
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However, a shape of the first wire is not a patentable subject matter: In accordance with MPEP 2144.04. I.B, referencing In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966), the court held that changes in shape is not patentable since this is a matter of choice of a person of ordinary skill in the art in absent persuasive evidence that the particular configuration is significant.
In re Claim 2, Ito/Watanabe teaches the semiconductor device of Claim 1 as cited above.
Ito/Watanabe further teaches (Annotated Modified Fig. 9) that, in the thickness direction, a farthest distance from the first electrode 22 to a portion of the covering portion 4 is larger than a distance from the first electrode 22 to a portion of the first portion of wire 3 that is the farthest from the first electrode 22 (the upper portion of 4 is higher than the upper portion of the first portion).
In re Claim 3, Ito/Watanabe teaches the semiconductor device of Claim 2 as cited above, wherein (Annotated Modified Fig. 9) the covering portion 4 covers at least a part of the first portion (of wire 3) from a side opposite to the semiconductor element 2 in the thickness direction.
In re Claim 4, Ito/Watanabe teaches the semiconductor device of Claim 1 as cited above, wherein (Annotated Modified Fig. 9) the first wire 3 includes a second portion – SP - that is linked to the first portion FP on a side opposite to the first electrode 22 and stands substantially upright in the thickness direction on a side away from the semiconductor element 2.
In re Claim 5, Ito/Watanabe teaches the semiconductor device according to Claim 1, wherein (Annotated Modified Fig. 9) the first wire 3 includes a bonding portion 31 joined to the first electrode 22 (paragraph 0037), and the first portion – FP - is integrally linked to the bonding portion 31
In re Claim 6, Ito/Watanabe teaches the semiconductor device according to Claim 1, wherein (Annotated Modified Fig. 9) the first wire 3 includes a bonding portion 31 joined to the first electrode 22, and the first portion FP is joined to the bonding portion 31.
In re Claim 7, Ito/Watanabe teaches the semiconductor device of Claim 1 as cited above, wherein (Annotated Modified Fig. 9, paragraph 0037 of Ito) the first portion FP is joined to the first electrode 22 (via portion 31).
In re Claim 8, Ito/Watanabe teaches the semiconductor device according to Claim 1, wherein (Annotated Modified Fig. 9) the covering portion 4 contains a metal – such as tin (Ito, paragraph 0045)
In re Claim 11, Ito/Watanabe teaches the semiconductor device according to Claim 8, wherein (Annotated Modified Fig. 9) the first electrode 22 contains Al (Ito, paragraph 0036).
In re Claim 12, Ito/Watanabe teaches the semiconductor device according to Claim 11, wherein (Annotated Modified Fig. 9) the first wire 3 contains Cu (paragraph 0037).
In re Claim 13, Ito/Watanabe teaches the semiconductor device according to Claim 1, wherein (Annotated Modified Fig. 9) the first electrode 22 includes a groove portion 23 (Ito, paragraph 0068) that is in contact with the covering portion 4.
In re Claim 14, Ito/Watanabe teaches the semiconductor device according to Claim 13, wherein (Annotated Modified Fig. 9) the first electrode 22 includes a first layer – as layer 22, and the groove portion 23 is formed by recessing a portion of the first layer 22.
In re Claim 18, Ito/Watanabe teaches the semiconductor device of Claim 1 as cited above, wherein (Annotated Modified Fig. 9) the first sire 3 includes a further bonding portion 31 joined to the first electrode 22, the first bonding portion 31 having a lower region LR held in direct contact with the first electrode 22 and an upper region UR opposite to the lower region LR in the thickness direction, the lower region LR being greater in area than the upper region UR.
In re Claim 19, Ito/Watanabe teaches the semiconductor device of Claim 18, wherein the first wire includes (Annotated Modified Fig. 9) an upright connecting portion UCP connecting the first portion FP and the first bonding portion 31 to each other.
In re Claim 20, Ito/Watanabe teaches the semiconductor device of Claim 1, wherein (Annotated Modified Fig. 9) the first portion FP includes a first part embedded in the covering portion 4 and a remaining part formed integral with the first part, the remaining part being exposed from the covering portion 4 and held in direct contact with the sealing region 5.
Claims 9-10 are rejected under 35 U.S.C. 103 as being unpatentable over Ito/Watanabe in view of Kajiwara et al. (US 2014/0264383).
In re Claim 9, Ito/Watanabe teaches the semiconductor device according to Claim 8 as cited above, including the covering portion that may contain metal (per paragraph 0045), but does not explicitly teach that the covering portion contains Ag or Cu.
Kajiwara teaches (Fig. 2) an electrode 1b separated from a sealing resin 14 (paragraph 0071) by a covering portion 16 comprised sintered Ag (paragraph 0057).
Ito/Watanabe and Kajiwara teach analogous arts directed to a semiconductor device comprised a semiconductor element covered by a sealing resin, and one of ordinary skill in the art before filing the application would have had a reasonable expectation of success in modifying the Ito/Watanabe device in view of Kajiwara device since they are from the same field of endeavor, and Kajiwara created a successfully functioning device.
It would have been obvious for one of ordinary skill in the art before filing the application to modify the Ito/Watanabe device by substituting its metallic material used for the covering portion with the sintered Ag (per Kajiwara), inherently having a higher thermal conductivity than the Ito sealing resin (as required by Claim 1), wherein such material is preferred for the manufacturer. See MPEP 2144.05 and MPEP 2143 on a Conclusion of Obviousness: KSR Rational (B): Simple Substitution of One Known Element for Another to Obtain Predictable Results. In addition, “It has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice”, In re Leshin, 125 USPQ 416.
In re Claim 10, Ito/Watanabe/Kajiwara teaches the semiconductor device according to Claim 9 as cited above and wherein the covering portion contains sintered Ag.
Claim 15 are rejected under 35 U.S.C. 103 as being unpatentable over Ito/Watanabe in view of Yu et al. (US 2008/0305306) and Yu et al. (US 2005/0077601) – Yu-1, hereafter.
In re Claim 15, Ito/Watanabe teaches the semiconductor device according to Claim 13 as cited above including the groove in the first electrode.
Ito/Watanabe further teaches (Annotated Modified Fig. 9) that the first electrode 22 includes a second layer (as aluminum alloy, paragraph 0036), and a first layer – such as coating, the second layer interposed between the element body and the first layer and is in contact with the first layer.
Ito/Watanabe does not teach that the groove portion is constituted by a slit formed in the first layer and the second layer is exposed from the slit.
Yu teaches (Figs. 4-5) a groove 70 formed layer 60 (paragraph 0031), where the groove is constituted by a slit (Abstract) extending along an edge of the layer.
Yu-1 teaches (paragraph 0158) that a patterned surface reduces a thermal resistance (and, accordingly, increases a heat flow between interfacing layers, e.g., increases a heat transfer; see also paragraphs 0055-0063).
Ito/Watanabe, Yu, and Yu-1 teach analogous arts directed to a groove in a layer or to a patterned surface, and one of ordinary skill in the art before filing the application would have had a reasonable expectation of success in modifying the Ito/Watanabe device in view of the Yu and Yu-1 teachings, since they are from the same field of endeavor and Yu and Yu-1 created successfully operated devices.
It would have been obvious for one of ordinary skill in the art before filing the application to modify the Ito/Watanabe device by creating each groove as a slit (per Yu) extending along a side of the electrode, wherein it is desirable to increase a heat transfer from the electrode (per Yu-1).
It would have been further obvious for one of ordinary skill in the art before filing the application (in view of Yu-1) that deeper slits allow a better heat transfer. In view of this, it would have been obvious for one of ordinary skill in the art before filing the first layer and to expose the second layer in the slit, if such slit is desirable for a better heat transfer from the first electrode.
Claims 16-17 are rejected under 35 U.S.C. 103 as being unpatentable over Ito/Watanabe in view of Yu.
In re Claim 16, Ito/Watanabe teaches the semiconductor device according to Claim 13, wherein (Annotated Modified Fig. 9) the groove portion 23 includes an outer peripheral portion – which is closest to a sidewall of electrode 22.
Ito/Watanabe does not teach that the groove extending along an outer edge of the first electrode.
Yu teaches (Figs. 4-5) a groove 70 formed layer 60 (paragraph 0031), where the groove extending along an edge of the layer 60.
It would have been obvious for one of ordinary skill in the art before filing the application to modify the groove of Ito per Yu allowing it to extend along the outer edge of the first electrode, if such shape of the groove is desired by the manufacturer. However, in accordance with MPEP 2144.04. I.B, referencing In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966), the court held that changes in shape is not patentable since this is a matter of choice of a person of ordinary skill in the art in absent persuasive evidence that the particular configuration is significant.
In re Claim 17, Ito/Watanabe/Yu teaches the semiconductor device according to Claim 16 as cited above.
Ito/Watanabe further teaches (Annotated Modified Fig. 9) that the groove portion includes an inner portion 23 located inward of the outer peripheral portion as viewed in the thickness direction.
Response to Arguments
Applicant’ arguments (REMARKS, filed 05/04/26) have been fully considered.
Examiner agrees with Applicant (REMARKS, pages 7-8) that amendments specification and claims remove grounds for objection to the drawings and specification of the application, as well as to rejections of the claims under 35 U.S.C. 112(b) presented by the Non-Final Rejection mailed 02/05/26.
Examiner agrees with the Applicant (REMARKS, pages 8-10) that the set of amended claims cannot be rejected using only prior arts cited by the Non-Final Rejection, but disagrees that the amended set of claims is patentable – the current Office Action shows that the amended set of claims is obvious over another combinations of prior arts.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication should be directed to GALINA G YUSHINA whose telephone number is 571-270-7440. The Examiner can normally be reached between 8 AM - 7 PM Pacific Time (Flexible).
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/GALINA G YUSHINA/Primary Patent Examiner, Art Unit 2811, TC 2800,
United States Patent and Trademark Office
E-mail: galina.yushina@USPTO.gov
Phone: 571-270-7440
Date: 05/16/26
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