DETAILED ACTION
This office action is in response to Application No. 18/480,372, filed on 3 October 2023. Claims 1-20 are pending.
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-5, 7, 8, 16-18, and 20 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Peng (“CAD Tools and Methodologies for Reliable 3D IC Design, Analysis, and Optimization”).
Regarding claim 1, Peng discloses a method, comprising: accessing a layout of a first die, wherein the first die is of a three-dimensional integrated circuit (3DIC) structure (p. 111, Fig. 64); generating a virtual design based on the layout of the first die, a first resistance and capacitance (RC) technology file (techfile) of the first die, and a second RC techfile of a second die, wherein the second die is of the 3DIC structure (p. 107, Fig. 61 and last sentence; p. 110, ¶¶2-3; p. 111, Figs. 63-64);
performing a virtual coupling capacitance extraction on the virtual design to form a virtual coupling capacitance netlist; and performing an static timing analysis on the first die with the virtual coupling capacitance netlist (p. 101, § 5.1.3; p. 111, Fig. 64; p. 115, § 5.5.1; p. 145, ¶2).
Regarding claim 2, Peng discloses that the step of generating the virtual design is free from using a 3DIC stack topology including a layout of the second die (p. 144, last par. to p. 145 ¶1).
Regarding claim 3, Peng discloses that the virtual design comprises virtual mirrored bump pattern and a virtual metal fill pattern (p. 5, § 1.2.4; p. 108, p. 109, Fig. 62, and p. 112, Fig. 66, F2F vias; p. 145, ¶1), and the virtual mirrored bump pattern and the virtual metal fill pattern act as a plurality of virtual signal nodes (p. 110, ¶¶2-3; p. 111, Figs. 64; p. 112, Fig. 66; p. 130, Fig. 70(b) and (c), and related text; p. 144, last par. to p. 145 ¶1).
Regarding claim 4, Peng discloses prior to performing the static timing analysis, annotating the virtual coupling capacitance netlist by the virtual signal nodes (p. 130, Fig. 70(b) and (c), and related text).
Regarding claim 5, Peng discloses that the virtual mirrored bump pattern has circular top view profiles, and the virtual metal fill pattern has rectangular top view profiles (p. 19, Fig. 8(a); p. 147, Fig. 76(a)).
Regarding claim 7, Peng discloses that the first die is configured to be bonded to the second die through a front-side of the first die, and the first die comprises a plurality of bumps and a plurality of metal pads/routings, the bumps and the metal pads/routings act as a plurality of signal nodes of the virtual coupling capacitance netlist (p. 2, Fig. 1(b); p. 5, § 1.2.4).
Regarding claim 8, Peng discloses that the first die is configured to be bonded to the second die through a back-side thereof, the first die comprises a metal layer, a bump, a substrate between the metal layer and the bump, and a through silicon via extending from the metal layer to the bump through the substrate, and the bumps act as a plurality of signal nodes of the virtual coupling capacitance netlist (p. 2, Fig. 1(a); p. 19, § 2.3.2 C4 bumps aligned with TSVs).
Regarding claim 16, Peng discloses a system, comprising: a capacitance extraction tool, generating a virtual design of a first die in a three-dimensional integrated circuit (3DIC) structure, wherein the generating is based on a first resistance and capacitance (RC) technology file of the first die, and a second RC techfile of a second die, and a layout of the second die, the second die is of the 3DIC structure and configured to stack with the first die (p. 107, Fig. 61 and last sentence; p. 110, ¶¶2-3; p. 111, Figs. 63-64);
a mesh generation engine, generating a virtual coupling capacitance netlist in response to the virtual design; and a static timing analysis tool, performing a simulation based on the virtual coupling capacitance netlist to account for a cross coupling capacitance between the first die and the second die (p. 101, § 5.1.3; p. 111, Fig. 64; p. 115, § 5.5.1; p. 145, ¶2).
Regarding claim 17, Peng discloses that the virtual design generated by the capacitance extraction tool determines positions of virtual capacitance nodes of the virtual coupling capacitance netlist (p. 110, ¶¶2-3; p. 111, Figs. 64; p. 112, Fig. 66; p. 130, Fig. 70(b) and (c), and related text; p. 144, last par. to p. 145 ¶1).
Regarding claim 18, Peng discloses that the virtual design generated by the capacitance extraction tool comprises virtual mirrored bump pattern and a virtual metal fill pattern (p. 5, § 1.2.4; p. 108, p. 109, Fig. 62, and p. 112, Fig. 66, F2F vias; p. 145, ¶1).
Regarding claim 20, Peng discloses that the simulation associated with the cross coupling capacitance is free from using a layout of the second die (p. 144, last par. to p. 145 ¶1).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 6 and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Peng in view of Cano (US 6,253,359).
Regarding claim 6, Peng discloses that the virtual design comprises a virtual mirrored bump pattern, and the virtual mirrored bump pattern act as a plurality of virtual signal nodes (p. 5, § 1.2.4; p. 108, p. 109, Fig. 62, and p. 112, Fig. 66, F2F vias; p. 145, ¶1), but does not appear to explicitly disclose a virtual silicon substrate ground plane. Cano discloses these limitations (col. 4, lines 25-30). It would have been obvious to persons having ordinary skill in the art before the effective filing date of the application to combine the teachings of Peng and Cano, because doing so would have involved merely the routine combination of known elements according to known techniques to produce merely the predictable results of accurately determining capacitance by accounting for the substrate ground plane. KSR Int’l Co. v. Teleflex Inc., 82 U.S.P.Q.2d 1385, 1395. Peng discloses capacitance extraction of a virtual design including virtual die elements. Cano teaches that the virtual die elements should include a virtual silicon substrate ground plane to accurately determine capacitance. The teachings of Cano are directly applicable to Peng in the same way, so that Peng would similarly include a virtual silicon substrate ground plane so that the capacitance extraction would accurately determine capacitance by accounting for the substrate ground plane.
Regarding claim 19, Peng does not appear to explicitly disclose that the virtual design generated by the capacitance extraction tool comprises a virtual ground plane pattern. Cano discloses these limitations (col. 4, lines 25-30); motivation to combine remains consistent with claim 6.
Claim(s) 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Peng in view of Fayyazi (“Deep Learning-Based Circuit Recognition Using Sparse Mapping and Level-Dependent Decaying Sum Circuit Representations”), and Xu (US 2023/0394641).
Regarding claim 9, Peng discloses prior to generating the virtual design, identifying a type of second die, the type of second die being of logic or memory (p. 144, last par.). Peng does not appear to explicitly disclose a machine learning algorithm; Fayyazi discloses these limitations (Abstract). Peng does not appear to explicitly disclose that the logic and memory dies are central processing unit (CPU), graphics processing unit (GPU), or high bandwidth memory (HBM); however, these are well-known types of logic and memory dies, as disclosed by Xu (¶49). It would have been obvious to persons having ordinary skill in the art before the effective filing date of the application to combine the teachings of Peng, Fayyazi, and Xu, because doing so would have involved merely the routine combination of known elements according to known techniques to produce merely the predictable results of identifying dies for more accurate extraction. KSR Int’l Co. v. Teleflex Inc., 82 U.S.P.Q.2d 1385, 1395. Peng discloses capacitance extraction for stacked dies using the identified die type to reconstruct a proxy for an unavailable die. Well-known die types include CPU, GPU, and HBM, as disclosed by Xu, and ML is well-known for identifying circuit function, as taught by Fayyazi. The teachings of Fayyazi and Xu are directly applicable to Peng in the same way, so that Peng would use well-known ML classification to identify well-known die types in order to improve the accuracy of the capacitance extraction for unavailable dies of well-known types.
Claim(s) 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Peng in view of Fayyazi, Xu, and Kang (US 11,836,435).
Regarding claim 10, Peng discloses determining a metal routing density of the virtual design, in response to the identified type of the second die (p. 144, last par.). As discussed above, Peng does not appear to explicitly disclose the artificial intelligence model, but such uses of AI models are known, as taught by Kang (col. 6, lines 28-29). It would have been obvious to persons having ordinary skill in the art before the effective filing date of the application to combine the teachings of Peng, Fayyazi, Xu, and Kang, because doing so would have involved merely the routine combination of known elements according to known techniques to produce merely the predictable results of using well-known ML/AI for determining density parameters to improve capacitance extraction accuracy. KSR Int’l Co. v. Teleflex Inc., 82 U.S.P.Q.2d 1385, 1395. Peng discloses capacitance extraction of stacked dies where a finished design of a die may be unavailable. Kang teaches that extraction accuracy can be improved by using ML to determine metal routing density when the routed design is unavailable (col. 3, lines 52-57). The teachings of Kang are directly applicable to Peng in the same way, so that Peng would similarly use ML/AI to determine metal routing density to improve capacitance extraction accuracy.
Claim(s) 11-13 and 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Peng in view of Huang (US 2017/0110425).
Regarding claim 11, Peng discloses a method, comprising: accessing a first layout of a first die (p. 111, Fig. 64); generating a first virtual design based on the first layout of the first die, a first resistance and capacitance (RC) technology file (techfile) of the first die, and a second RC techfile of a structure (p. 107, Fig. 61 and last sentence; p. 110, ¶¶2-3; p. 111, Figs. 63-64);
performing a first virtual coupling capacitance extraction on the first virtual design to form a first virtual coupling capacitance netlist; and performing a first static timing analysis on the first die with the first virtual coupling capacitance netlist (p. 101, § 5.1.3; p. 111, Fig. 64; p. 115, § 5.5.1; p. 145, ¶2).
Peng does not appear to explicitly disclose an integrated fan-out (InFO) structure; however, InFO structures connected to dies are well-known, as taught by Huang (¶1). It would have been obvious to persons having ordinary skill in the art before the effective filing date of the application to combine the teachings of Peng and Huang, because doing so would have involved merely the routine combination of known elements according to known techniques to produce merely the predictable results of determining coupling capacitance of dies connected to InFO structures. KSR Int’l Co. v. Teleflex Inc., 82 U.S.P.Q.2d 1385, 1395. Peng teaches capacitance extraction for stacked devices such as IC dies. InFO packages are well-known for stacking dies with structures such as redistribution layers (RDLs), as taught by Huang. The teachings of Huang are directly applicable to Peng in the same way, so that Peng’s process would be used to perform capacitance extraction for InFO packages.
Regarding claim 12, Peng discloses that the first virtual design comprises a virtual mirrored bump pattern and a first virtual metal layer including a first virtual metal fill pattern (p. 5, § 1.2.4; p. 108, p. 109, Fig. 62, and p. 112, Fig. 66, F2F vias; p. 145, ¶1), the virtual mirrored bump pattern and the first virtual metal fill pattern act as a plurality of first virtual signal nodes of the first virtual coupling capacitance netlist (p. 110, ¶¶2-3; p. 111, Figs. 64; p. 112, Fig. 66; p. 130, Fig. 70(b) and (c), and related text; p. 144, last par. to p. 145 ¶1). Peng does not appear to explicitly disclose under bump metallurgy (UBM) and redistribution layers, but these are well-known aspects of InFO packages, as taught by Huang (¶1). Motivation to combine remains consistent with claim 11.
Regarding claim 13, Peng discloses that the first virtual design comprises a second virtual metal layer at different level height than the first virtual metal layer, the second virtual metal layer comprises a second virtual metal fill pattern, the second virtual metal fill pattern acts as a plurality of second virtual signal nodes of the first virtual coupling capacitance netlist (p. 145, ¶1). As discussed above, Peng does not appear to explicitly disclose redistribution layers, but these are well-known aspects of InFO packages, as taught by Huang (¶1). Motivation to combine remains consistent with claim 11.
Regarding claim 15, Peng discloses accessing a second layout of a second die; generating a second virtual design based on the second design of the second die, the second RC techfile of the structure, and a third RC techfile of the second die; performing a second virtual coupling capacitance extraction on the second virtual design to form a second virtual coupling capacitance netlist; and performing a second static timing analysis on the second die with a second netlist of the second die, along with the second virtual coupling capacitance netlist. Specifically, these limitations merely repeat claim 11 with another die, and Peng is explicitly an analysis process that can be performed on arbitrary dies (p. 145 logic-memory and logic-logic; p. 149 Fig. 78 dies of various technology nodes, etc.). Furthermore, repeating/duplicating elements is likely to be obvious; see MPEP § 2144.04(VI)(B). As discussed above, Peng does not appear to explicitly disclose the InFO structure, which is taught by Huang (¶1); the reasoning applied to claim 11 similarly applies here, and motivation to combine remains consistent with claim 11.
Claim(s) 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Peng in view of Huang and Shenjoy (US 5,994,766).
Regarding claim 14, Peng discloses that the first virtual metal fill pattern comprises a plurality of metal lines, and a pitch of the metal lines is set to an established pitch (p. 145, ¶1), but does not appear to explicitly disclose minimum pitch established in a design rule of the InFO structure. However, as discussed above, well-known InFO packages connect to IC dies through metal routing in redistribution layers, as taught by Huang (¶1), and such redistribution layers follow well-known design rules that define minimum pitch, width, etc., as taught by Shenjoy (col. 8, lines 12-17). It would have been obvious to persons having ordinary skill in the art before the effective filing date of the application to combine the teachings of Peng, Huang, and Shenjoy, because doing so would have involved merely the routine combination of known elements according to known techniques to produce merely the predictable results of determining capacitance based on realistic design parameters. KSR Int’l Co. v. Teleflex Inc., 82 U.S.P.Q.2d 1385, 1395. Peng teaches capacitance extraction for stacked devices such as IC dies. InFO packages are well-known for stacking dies with structures such as redistribution layers (RDLs), as taught by Huang, and the RDLs follow well-known design rules, as taught by Shenjoy. The teachings of Shenjoy are directly applicable to Peng in the same way, so that Peng’s capacitance extraction process would operate on designs adhering to design rules, in order to determine capacitance based on realistic design parameters.
Conclusion
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11 August 2026
/ARIC LIN/ Examiner, Art Unit 2851
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