DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group (claims 1-8) in the reply filed on 12/30/2025 is acknowledged.
Claims 9-14 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Group II, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 12/30/2025.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 2, 7, and 8 are rejected under 35 U.S.C. 102(a)(1)/(a)(2) as being anticipated by Liu (US 2017/0098589).
Regarding claim 1, Liu discloses a semiconductor device comprising: a semiconductor chip (Fig.1, numeral 200) in which a bonding pad (203) is formed in a wafer state (note: “is formed in a wafer state” is a product-by-process limitaiton...); a first passivation layer (205) formed on the semiconductor chip (200)to expose the bonding pad (203); a first re-distribution layer (102) connected to the bonding pad (203) and extending on the first passivation layer; (205) a conductive bump (122) disposed on an electrical signal path leading to the bonding pad (203), the first re-distribution layer (102), and a substrate ([0021]); and a capacitor (120) formed to be electrically connected ([0029]) to the first re-distribution layer (102) at a wafer level ([0020]) before the conductive bump (120) is formed (note: “before the conductive bump is formed” is a product-by-process limitation. And according to MPEP 2113, I “"[E]ven though product-by-process claims are limited by and defined by the process, determination of patentability is based on the product itself. The patentability of a product does not depend on its method of production. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process." In re Thorpe, 777 F.2d 695, 698, 227 USPQ 964, 966 (Fed. Cir. 1985)).
Regarding claim 2, Liu discloses wherein the bonding pad includes first and second bonding pads (Fig.1, numeral 203), the first passivation layer (205) is formed on the semiconductor chip (200) to expose the first and second bonding pads (203), the first re-distribution layer includes first and second re-distribution lines (102b) which are respectively connected to the first and second bonding pads (203) and extend on the first passivation layer (205); the conductive bump (122) includes a first conductive bump disposed on a first electrical signal path leading to the first bonding pad (203), the first re-distribution line (102a), and the substrate ([0022]) and a second conductive bump (122) disposed on a second electrical signal path leading to the second bonding pad (203), the second re-distribution line (102a), and the substrate, and the capacitor (120) is electrically connected to the first and second re-distribution lines (102a) and disposed between the first and second conductive bumps (122) (Fig.1).
Regarding claim 7, Liu discloses wherein the conductive bump is implemented as a solder bump or a Cu pillar bump ([0023]).
Regarding claim 8, Liu discloses the semiconductor device of claim 1, wherein the semiconductor device is implemented as a wafer-level package (WLP) or a wafer-level chip-scale package (WLCSP) ([0020]).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 3 and 5 are rejected under 35 U.S.C. 103 as being unpatentable over Liu as applied to claim 2 above, and further in view of Lin (US 2016/0268234).
Regarding claim 3, Liu discloses: a second passivation layer formed on the first passivation layer (Fig.1, numeral 102a; note: lowest ILD layer; [0027]) and the first re-distribution layer (102b) to expose at least a part of the first re-distribution layer (102a); and wherein the first and second conductive bumps (122).
Liu does not explicitly disclose a conductive member formed in a region in which the first re-distribution layer is exposed through the second passivation layer, that the capacitor is formed on and in contact with the conductive member.
Lin however discloses that a conductive member (Fig.1, 324, 326) formed in a region in which the first re-distribution layer (210) is exposed through the second passivation layer (320), the capacitor (Fig.1, numeral 330) is formed on and in contact with the conductive member (324), (326).
It would have been therefore obvious to one of ordinary skill in the art at the time the invention was filed to modify Liu with Lin to have a conductive member formed in a region in which the first re-distribution layer is exposed through the second passivation layer, that the capacitor is formed on and in contact with the conductive member for the purpose of improving signal integrity performance of the semiconductor package assembly (Lin, [0025]).
Regarding claim 5, Liu discloses a second passivation layer formed on the first passivation layer and the first re-distribution layer to expose at least a part of the first re-distribution layer; a second re-distribution layer formed in a region in which the first re- distribution layer is exposed through the second passivation layer; a third passivation layer formed on the second passivation layer and the second re-distribution layer to expose at least a part of the second re-distribution layer
Liu does not explicitly disclose a conductive member formed in a region in which the second re-distribution layer is exposed through the third passivation layer, wherein the first and second conductive bumps and the capacitor are formed on and in contact with the conductive member.
Lin however discloses that a conductive member (Fig.1, 324, 326, 328) formed in a region in which the first re-distribution layer (210) is exposed through the third passivation layer (320), wherein the first and second conductive bumps (322) and the capacitor (Fig.1, numeral 330) are formed on and in contact with the conductive member (324), (326), (328).
It would have been therefore obvious to one of ordinary skill in the art at the time the invention was filed to modify Liu with Lin to have a conductive member formed in a region in which the second re-distribution layer is exposed through the third passivation layer, wherein the first and second conductive bumps and the capacitor are formed on and in contact with the conductive member for the purpose of improving signal integrity performance of the semiconductor package assembly (Lin, [0025]).
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Liu as applied to claim 2 above, and further in view of KR’893 (KR10-2008-0068983, Machine Translation is provided).
Regarding claim 4, Liu discloses a second passivation layer (Fig.5, lower IMD layer [0027]) formed on the first passivation layer (205) and the first re-distribution layer (102) to expose at least a part of the first re-distribution layer (102b).
Liu does not disclose (1) a second re-distribution layer formed in a region in which the first re- distribution layer is exposed through the second passivation layer; a third passivation layer formed on the second passivation layer and the second re-distribution layer to expose at least a part of the second re-distribution layer; and a conductive member formed in a region in which the second re-distribution layer is exposed through the third passivation layer and the first and second conductive bumps are formed on and in contact with the conductive member; (2) wherein the capacitor is formed on and in contact with the first re- distribution layer between the first passivation layer and the third passivation layer.
Regarding elements (1), Liu discloses forming multiple IMD layers (102a) and multiple conductive traces (102b) ([0027]). Liu further discloses forming a conductive member in a region in which the re-distribution layer is exposed through the passivation layer and the first and second conductive bumps are formed on and in contact with the conductive member (Fig.5).
It would have been therefore obvious to one of ordinary skill in the art at the time the invention was file to form a second re-distribution layer formed in a region in which the first re- distribution layer is exposed through the second passivation layer; a third passivation layer formed on the second passivation layer and the second re-distribution layer to expose at least a part of the second re-distribution layer; and a conductive member formed in a region in which the second re-distribution layer is exposed through the third passivation layer and the first and second conductive bumps are formed on and in contact with the conductive member for the purpose of forming RDL structure (Liu, [0027]).
Regarding elements (2), KR’893 however discloses wherein the capacitor is formed on and in contact with the first re- distribution layer between the first passivation layer and the third passivation layer ([0033]; Fig. 2).
It would have been therefore obvious to one of ordinary skill in the art at the time the invention was filed to modify Liu with KR’893 to have the capacitor is formed on and in contact with the first re- distribution layer between the first passivation layer and the third passivation layer for the purpose of saving manufacturing cost (KR’983, [0031]).
Claim(s) 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Liu as applied to claim 2 above, and further in view of Zhu (US 2014/0225223).
Regarding claim 6, Liu discloses, and the first re-distribution line (102b) or the second re-distribution line (102b) is formed to be electrically connected to an additional conductive bump (122) in addition to the first conductive bump or the second conductive bump (Fig.5).
Liu does not disclose wherein the first and second re- distribution lines function as multi-nodes of the capacitor.
Zhu however discloses that the first and second re- distribution lines function as multi-nodes of the capacitor ([0031]).
It would have been therefore obvious to one of ordinary skill in the art at the time the invention was filed to modify Liu with Zhu to have that the first and second re- distribution lines function as multi-nodes of the capacitor for the purpose of reducing the number of processing steps (Zhu, Abstract).
Conclusion
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/JULIA SLUTSKER/Primary Examiner, Art Unit 2891