DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Examiner notes that claims 10 and 15-20 were cancelled in the response filed 3/11/2026.
Election/Restrictions
Applicant’s election without traverse of Invention I, Species V (claims 1-9 and 11-14) in the reply filed on 3/11/2026 is acknowledged.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Claim Objections
Claim 13 is objected to because of the following informalities: in lines 3-4, "the third portion is connected with the third portion" should be amended to read -the fourth portion is connected with the third portion-. Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim 1 is rejected under 35 U.S.C. 103 as being unpatentable over Lu et al (US 2022/0328611 and Lu hereinafter) in view of Matsushima (US 2012/0091440 and Matsushima hereinafter) with supporting evidence from Sakakibara (US 2026/0049244 and Sakakibara hereinafter).
Lu discloses a display panel (Figs. 14a-14c; [0273]), comprising: an array substrate (Fig. 14c) comprising: a carrier board (substrate; [0150] and [0273]); a dielectric layer stack (85 comprises at least an interlayer insulating layer, which is interpreted to be the claimed dielectric layer stack; [0150]-[0151]) over the carrier board (substrate); a first electrode pad (lower half of 4; [0150] and [0273]) over the dielectric layer stack (interlayer insulating layer within 85; [0150]-[0151] and [0273]); and a second electrode pad (6; [0273]) over the dielectric layer stack (interlayer insulating layer within 85) and adjacent to the first electrode pad (4), and the first electrode pad (lower half of 4) and the second electrode pad (6) provide different potentials (Fig. 1a; 6 is connected to VSS and 4 is connected to VDD; [0111], [0391], and [0409]); a light-emitting diode chip (“G” area comprises the organic light emitting material layer 83; [0158]) comprising a first electrode (upper half of 4; [0150] and [0273]) and a second electrode (51 over “G” area; [0273]) at opposite sides (top and bottom) of the light-emitting diode chip (“G” area comprises the organic light emitting material layer 83), and the first electrode (upper half of 4) connected with the first electrode pad (lower half of 4); a first material layer (80; [0132]) over the array substrate and surrounding the light-emitting diode chip (“G” area), wherein the first material layer (80) comprises an opening (in which 51 is formed) exposing the second electrode pad (6), and a first conductive layer (51 outside of “G” area overlap; [0273]) over the first material layer (80) and electrically connecting the second electrode pad (6) and the second electrode (51 over “G” area).
Lu fails to expressly disclose where the first material layer is a photosensitive material layer; where a sidewall of the opening of the first photosensitive material layer has a first portion and a second portion, a first slope of the first portion of the sidewall of the opening of the first photosensitive material layer is greater than a second slope of the second portion of the sidewall of the opening of the first photosensitive material layer, and a vertical projection of the first portion of the sidewall of the opening of the first photosensitive material layer on the array substrate is smaller than a vertical projection of the second portion of the sidewall of the opening of the first photosensitive material layer on the array substrate; where the first conductive layer is transparent.
Lu discloses that the first material layer is a pixel defining layer, see [0132].
Matsushima discloses a display device with a bank/pixel defining layer 605, see Fig. 17A and [0209], where the first material layer (Fig. 17A; 605; [02209]) is a photosensitive material layer (105/605 can comprise an acrylic resin or polyimide resin, which are photosensitive materials as disclosed by Sakakibara in [0027]; [0119] of Matsushima); where a sidewall of the opening (shown in Fig. 17A as the segmented sidewall of 605 over 104) of the first photosensitive material layer (605) has a first portion (P61-P62; [0209]) and a second portion (P62-P63; [0209]), a first slope of the first portion (P61-P62) of the sidewall of the opening of the first photosensitive material layer (605) is greater (since θy1 is greater than θy2, the slope of P61-P62 is greater than that of P62-P63; [0209]) than a second slope of the second portion (P62-P63) of the sidewall of the opening of the first photosensitive material layer (605), and a vertical projection (length of P61-P62 onto 104) of the first portion (P61-P62) of the sidewall of the opening of the first photosensitive material layer (605) on the array substrate (104) is smaller (length of P61-P62 is smaller than that of P62-P63) than a vertical projection (length of P62-P63 onto 104) of the second portion (P62-P63) of the sidewall of the opening of the first photosensitive material layer (605) on the array substrate (104); where the first conductive layer (Fig. 2; 108 is a cathode layer; [0128]) is transparent (108 is transparent; [0130]).
Given the teachings of Matsushima with supporting evidence from Sakakibara, a person having ordinary skill in the art before the effective filing date of the claimed invention would have readily recognized the desirability and advantages of modifying Lu by employing the well-known or conventional features of display fabrication, such as displayed by Matsushima with supporting evidence from Sakakibara, by employing a photosensitive bank material that comprises multiple sections with different slopes and lengths as claimed and a transparent material for the cathode layer in order to provide a means to provide uniform film thickness in the organic light-emitting layer across the entire panel ([0009[) and to increase light extraction efficiency ([0131]).
Claims 9, 11, and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Lu in view of Tsuruoka (US 2019/0165078 and Tsuruoka hereinafter) in view of Matsushima with supporting evidence from Sakakibara.
As to claims 9, 11, and 13: Lu discloses [claim 9] a display panel (Figs. 14a-14c; [0273]), comprising: an array substrate (Fig. 14c) comprising: a carrier board (substrate; [0150] and [0273]); an active component (Fig. 3; transistor T5; [0100]) over the carrier board (substrate); a dielectric layer stack (85 comprises at least an interlayer insulating layer, which is interpreted to be the claimed dielectric layer stack; [0150]-[0151]) over the active component (transistor T5) and the carrier board (substrate); a first electrode pad (lower half of 4; [0150] and [0273]) over the dielectric layer stack (interlayer insulating layer within 85; [0150]-[0151] and [0273]) and connected with the active component (as shown in Fig. 3, the anode of the OLED is connected to T5); and a second electrode pad (6; [0273]) over the dielectric layer stack (interlayer insulating layer within 85) and adjacent to the first electrode pad (4); a light-emitting diode chip (“G” area comprises the organic light emitting material layer 83; [0158]) comprising a first electrode (upper half of 4; [0150] and [0273]) and a second electrode (51 over “G” area; [0273]) at opposite sides (top and bottom) of the light-emitting diode chip (“G” area comprises the organic light emitting material layer 83), and the first electrode (upper half of 4) connected with the first electrode pad (lower half of 4); a first material layer (81; [0126]) over the array substrate and surrounding the light-emitting diode chip (81 is formed such that it extends beyond the edges of the “G” area and the electrode 4 and thus surrounds the chip from underneath), wherein the first material layer (81) comprises an opening (in which 51 is formed) exposing the second electrode pad (6); a first transparent conductive layer (Fig. 4a; 10 can be the same material as 4, which comprises an ITO layer, which is transparent; [0318] and [0112]) over the first material layer (81) and in contact with the second electrode pad (6); a second material layer (80; [0132]) over the first material layer (81) and surrounding the light-emitting diode chip (“G” area), wherein the second material layer (80) comprises an opening (in which 51 is formed) exposing the second electrode pad (6) and a portion of the first material layer (81); and a second conductive layer (Figs. 4c and 18; 51; [0273]) over the second material layer (80) and the first transparent conductive layer (10); [claim 11] wherein the first transparent conductive layer (Fig. 18; 10) is between the first material layer (81) and the second material layer (80).
Lu fails to expressly disclose where [claims 9 and 11] the first material layer is a photosensitive material layer.
Lu discloses that the first material layer 81 is a planarization layer, see [0275].
Tsuruoka discloses a display device and states that planarization layers, such as layer 102 in Fig. 10, can comprise a photosensitive acrylic resin, see [0035].
Given the teachings of Tsuruoka, a person having ordinary skill in the art before the effective filing date of the claimed invention would have readily recognized the desirability and advantages of modifying Lu by employing the well-known or conventional features of display device fabrication, such as displayed by Tsuruoka, by employing a photosensitive acrylic resin as the planarization layer 81 in order to provide a material that can provide a flat upper surface ([0035]).
Lu in view of Tsuruoka fail to expressly disclose [claims 9 and 11] where the second material layer is a photosensitive material; where the second conductive layer is transparent; [claim 12] wherein a sidewall of the opening of the first photosensitive material layer has a first portion and a second portion, the first portion is closer to the second electrode pad, the second portion is farther away from the second electrode pad, a first slope of the first portion of the sidewall of the opening of the first photosensitive material layer is greater than a second slope of the second portion of the sidewall of the opening of the first photosensitive material layer.
Matsushima discloses a display device with a bank/pixel defining layer 605, see Fig. 17A and [0209], [claims 9 and 11] where the second material layer (Fig. 17A; 605; [02209]) is a photosensitive material layer (105/605 can comprise an acrylic resin or polyimide resin, which are photosensitive materials as disclosed by Sakakibara in [0027]; [0119] of Matsushima); where the second conductive layer (Fig. 2; 108 is a cathode layer; [0128]) is transparent (108 is transparent; [0130]); [claim 12] wherein a sidewall of the opening (shown in Fig. 17A as the segmented sidewall of 605 over 104) of the first photosensitive material layer (605) has a first portion (P61-P62; [0209]) and a second portion (P62-P63; [0209]), the first portion (P61-P62) is closer to the second electrode pad (6), the second portion (P62-P63) is farther away from the second electrode pad (6), a first slope of the first portion (P61-P62) of the sidewall of the opening of the first photosensitive material layer (605) is greater (since θy1 is greater than θy2, the slope of P61-P62 is greater than that of P62-P63; [0209]) than a second slope of the second portion (P62-P63) of the sidewall of the opening of the first photosensitive material layer (605).
Given the teachings of Matsushima with supporting evidence from Sakakibara, a person having ordinary skill in the art before the effective filing date of the claimed invention would have readily recognized the desirability and advantages of modifying Lu by employing the well-known or conventional features of display fabrication, such as displayed by Matsushima with supporting evidence from Sakakibara, by employing a photosensitive bank material that comprises multiple sections with different slopes as claimed and lengths and a transparent material for the cathode layer in order to provide a means to provide uniform film thickness in the organic light-emitting layer across the entire panel ([0009[) and to increase light extraction efficiency ([0131]).
Allowable Subject Matter
Claims 2-8, 13, and 14 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims and if claim 13 is rewritten to overcome the claim objection noted above.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JOSEPH C NICELY whose telephone number is (571)270-3834. The examiner can normally be reached Monday-Friday 7:30 am - 4 pm, EST.
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JOSEPH C. NICELY
Primary Examiner
Art Unit 2813
/JOSEPH C. NICELY/Primary Examiner, Art Unit 2813
4/17/2026
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