DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 10/23/2025 has been entered.
Claim Status
3. Claims 6, 13-14, and 22-23 are now canceled; Claims 24-25 are newly-added; Claims 1-5, 7-12, and 15-21, and 24-25 remain pending in the application.
4. Claims 1-5, 7-12, 15-21, and 24-25 have been fully considered in examination.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-5, 7, and 24-25 are rejected under 35 U.S.C. 103 as being unpatentable over Lin (U.S. PG Pub No US2017/0345944A1) (of record) in view of Lin-II (U.S. PG Pub No US2019/0378715A1) (of record) and Hiramatsu (U.S. PG Pub No US2014/0346497A1) (of record).
Regarding claim 1, Lin teaches a semiconductor device (200) fig. 11 [0048], comprising:
a substrate (102) fig. 11 [0049];
a two-dimensional (2-D) material semiconductor layer (204) fig. 11 [0048] (TMD film [0048]) ([0002, 0014, 0018, 0024] discloses that the TMD/graphene materials in 110 stack are 2-D materials) over the substrate (102);
source/drain electrodes (comprising 112/114 and 202, 192 in direct contact) fig. 11 [0048-0049] horizontally spaced apart from each other (at least 112 and 114 horizontally spaced apart), wherein each of the source/drain electrodes comprises a 2-D material semimetal layer (202, 192 in direct contact with 112/114) fig. 11 [0048] (could be TMD or graphene [0051]) and a metal (112/114 comprising titanium/gold films) [0027] over the 2-D material semimetal layer (202, 192);
a first gate dielectric layer (lower half of 116) fig. 11 [0046] in direct contact with the 2-D material semiconductor layer (204);
a second gate dielectric layer (upper portion of 116 - also in 116; 116 may represent two or more dielectric films) fig. 11 [0029] over the first gate dielectric layer (lower half of 116) fig. 11 [0029, 0046]; and
a gate electrode (118) fig. 11 [0046] over the second gate dielectric layer (upper portion of 116).
However, Lin does not explicitly disclose 2-D material layers covering opposite sides of the 2-d material semiconductor layer and horizontally spaced apart from each other,
source/drain electrodes (comprising 112/114) over the 2-d material layers and horizontally spaced apart from each other,
a first gate dielectric layer (116) in direct contact with the source/drain electrodes (comprising 112, 114),
and the second gate dielectric layer (upper portion of 116) forms an interface with the first gate dielectric layer (lower half of 116 – implied but not shown), wherein the first gate dielectric layer (lower half of 116) and the second gate dielectric layer (upper half of 116) are made of a same material [0029],
wherein the first gate dielectric layer (lower half of 116) has a stepped top surface and the second gate dielectric layer (upper half of 116) has an uppermost top surface that is coplanar and interfaces with the gate electrode (118).
Lin-II teaches a semiconductor device (800) fig. 8 [0057] comprising 2-D material layers (right/left 720) fig. 8 [0044-0045] covering opposite sides of the 2-d material semiconductor layer (620) fig. 8 [0044] and horizontally spaced apart from each other,
source/drain electrodes (comprising right/left 730) fig. 8 [0046] over the 2-d material layers (right/left 720) and horizontally spaced apart from each other (720s and 730s horizontally spaced apart from each other).
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified the transistor of Lin such that individual of the source and drain electrodes are paired with horizontally separated 2-D material layers [0044-0046] in order to improve the conductivity of the source/drain electrode stacks [0013-0014, 0044] and enhance crystalline properties of device materials [0047], as taught by Lin-II.
However, Lin in view of Lin-II does not explicitly disclose a first gate dielectric layer (116) in direct contact with the source/drain electrodes (comprising 112, 114),
and the second gate dielectric layer (upper portion of 116) forms an interface with the first gate dielectric layer (lower half of 116 – implied but not shown), wherein the first gate dielectric layer (lower half of 116) and the second gate dielectric layer (upper half of 116) are made of a same material [0029],
wherein the first gate dielectric layer (lower half of 116) has a stepped top surface and the second gate dielectric layer (upper half of 116) has an uppermost top surface that is coplanar and interfaces with the gate electrode (118).
Hiramatsu teaches a semiconductor device [see fig. 2, 0022] comprising a first gate dielectric layer (31) fig. 2 [0024] in direct contact with the source/drain electrodes (right/left 60) fig. 2 [0026]; and
the second gate dielectric layer (32) fig. 2 [0024] forms an interface with the first gate dielectric layer (31), wherein the first gate dielectric layer (31) and the second gate dielectric layer (32) are made of a same material (both made of/from silicon dioxide) [0024],
wherein the first gate dielectric layer (31) has a stepped top surface (stepped over channel layer 20) [0024] and the second gate dielectric layer (32) has an uppermost top surface that is coplanar and interfaces with the gate electrode (40) fig. 2 [0025].
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified the transistor structure of Lin in view of Lin-II such that it adopts dual-layer gate dielectric structure [0024-0025] of Hiramatsu in order to effectively form a stepped gate insulating layer [0018, 0020, 0024] capable of providing sufficient insulation between the gate electrode, channel, and source/drain electrodes [0024-0025] in the TFT, as taught by Hiramatsu.
Regarding claim 2, Lin in view of Lin-II and Hiramatsu teaches the semiconductor device (200) fig. 11 [0048] of claim 1. Lin also teaches wherein the 2-D material semimetal layer (202, 192 in direct contact with 112/114) fig. 11 [0048] (could be TMD or graphene [0051]) is thinner than the metal (112/114 comprising titanium/gold films) [0027] (202, 204 clearly thinner than 112, 114 as measured from top to bottom in fig. 11).
Regarding claim 3, Lin in view of Lin-II and Hiramatsu teaches the semiconductor device (200) fig. 11 [0048] of claim 1. Lin also teaches wherein the first gate dielectric layer (lower portion of 116) fig. 11 [0046] is in (thermal/electrical) contact with the 2-D material semimetal layer (202, 192 in direct contact with 112/114) fig. 11 [0048] (could be TMD or graphene [0051]) of the source/drain electrodes (comprising 112/114, 202, 192) fig. 11 [0049].
Regarding claim 4, Lin in view of Lin-II and Hiramatsu teaches the semiconductor device (200) fig. 11 [0048] of claim 1. Lin in view of Hiramatsu (with reference to Hiramatsu) also teaches wherein the first gate dielectric (31) fig. 2 [0024] is thinner (10nm thickness) [0031] than the second gate dielectric (32) fig. 2 [0024] (70 nm thickness) [0032] (31 could have 10 nm thickness [0031] while 32 has a thickness of 70 nm [0032]).
Regarding claim 5, Lin in view of Lin-II and Hiramatsu teaches the semiconductor device (200) fig. 11 [0048] of claim 1. Lin in view of Hiramatsu (with reference to Hiramatsu) also teaches wherein a thickness of the second gate dielectric layer (31) fig. 2 [0024] is in a range from about 5 nm to about 30 nm (Hiramatsu teaches that a gate dielectric layer [0024, 0031] such as the second gate dielectric layer of Lin may have thickness of 10 nm [0031]).
Regarding claim 7, Lin in view of Lin-II and Hiramatsu teaches the semiconductor device (200) fig. 11 [0048] of claim 1. Lin in view of Lin-II (with reference to Lin-II) also teaches wherein the 2-D material layers (right/left 720) fig. 8 [0044-0045] are made of graphene (“semimetal” used [0057, 0060, 0013-0014]; graphene could be used as the semimetal [0002 Lin-II]).
Regarding claim 22, Lin in view of Lin-II and Hiramatsu teaches the semiconductor device (200) fig. 11 [0048] of claim 1. Lin also teaches wherein opposite sidewalls of the 2-D material semimetal layer (202, 192 in direct contact with 112/114) fig. 11 [0048] (could be TMD or graphene [0051]) of each of the source/drain electrodes (comprising 112/114 and 202, 192 in direct contact) fig. 11 [0048-0049] are in (thermal) contact with the (bottom of) first gate dielectric layer (lower half of 116) fig. 11 [0046] (through attached thermally conductive layers TMD [0048] of the transistor).
Regarding claim 24, Lin in view of Lin-II and Hiramatsu teaches the semiconductor device (200) fig. 11 [0048] of claim 1. Lin also teaches wherein the uppermost top surface of the second gate dielectric layer (upper portion of 116 - also in 116; 116 may represent two or more dielectric films) fig. 11 [0029] spans over the source/drain electrodes (comprising 112/114, 202, 192) fig. 11 [0048-0049]
Regarding claim 25, Lin in view of Lin-II and Hiramatsu teaches the semiconductor device (200) fig. 11 [0048] of claim 1. Lin also teaches wherein the metal (112/114) of each of the source/drain electrodes (comprising 112/114 and 202, 192 in direct contact) fig. 11 [0048-0049] interfaces with a top (peripheral) surface of the 2-D material semimetal layer (202, 192 in direct contact with 112/114) fig. 11 [0048].
Claims 8-12 are rejected under 35 U.S.C. 103 as being unpatentable over Lin (U.S. PG Pub No US2017/0345944A1) (of record) in view of Lin-II (U.S. PG Pub No US2020/0006541A1) (of record), Kim (U.S. PG Pub No US2009/0101911A1) (of record), and Kim (U.S. PG Pub No US2019/0164754A1) (of record).
Regarding claim 8, Lin teaches a semiconductor device (200) fig. 11 [0048], comprising:
a substrate (102) fig. 11 [0049];
a two-dimensional (2-D) material semiconductor layer (106) fig. 11 [0048] (TMD film [0047-0048]) ([0002, 0014, 0018, 0024] discloses that the TMD/graphene materials in 110 stack are 2-D materials) over the substrate (102);
(a) 2-D material layer (204) fig. 11 [0048] (TMD films [0048] or graphene [0051]) covering opposite sides of the 2-D material semiconductor layer (106), wherein the 2-D material layer (204) is/are made of graphene [0051] (or alternatively TMD [0048, 0051]);
source/drain electrodes (comprising 112/114 and 108, 192 in direct contact) fig. 11 [0048-0049] over the 2-D material layer(s) (204), respectively, wherein the 2-D material layers (individual graphene layers of 204) [0048] are thinner than the source/drain electrodes (112/114 s/d electrodes stretch vertically across and beyond entire-thickness of 204-material);
a first gate dielectric layer (116) fig. 11 [0046] covering the 2-D material semiconductor layer (106) and the source/drain electrodes (comprising 108, 192);
a second gate dielectric layer (upper portion of - also in 116; 116 may represent two or more dielectric films) fig. 11 [0029] over the first gate dielectric layer (lower half of 116) fig. 11 [0029, 0046]; and
a gate electrode (118) fig. 11 [0046] over the second gate dielectric layer (upper portion of 116).
However, Lin does not explicitly disclose multiple 2-d material layers (204) covering opposite sides of the 2-d material semiconductor layer (106) and horizontally spaced apart from each other, wherein the 2-d material layers are made of graphene; and
and the second gate dielectric layer (upper portion of 116) forms an interface with the first gate dielectric layer (lower half of 116 – implied but not shown), wherein the first gate dielectric layer (lower half of 116) and the second gate dielectric layer (upper half of 116) are made of a same material [0029],
and wherein the gate electrode vertically overlaps the (horizontally spaced apart) 2-d material layers (204).
Lin-II teaches a semiconductor device (300) fig. 2H [0056] further comprising multiple 2-D material layers (230(1), 230(2)) fig. 2H [0050-0054] covering opposite sides of the 2-D material semiconductor layer (222) fig. 2H [0056] (MoS2 film [0056]) and horizontally spaced apart from each other, wherein the 2-D material layers (230(1), 230(2)) are made of graphene (“any 2-D material” different from the first [0037 Lin-II]; [0001-0002, 0051] of Lin discloses graphene as a 2-D material).
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified the transistor device of Lin to include the multiple, horizontally-spaced 2-D material layers of Lin-II intervening the source/drain metal and 2-D semiconductor layer [0051-0059] in order to desirably tune the conductivity properties of the source/drain electrodes [0009, 0045], as taught by Lin-II.
Still, Lin in view of Lin-II does not explicitly disclose and the second gate dielectric layer (upper portion of 116) forms an interface with the first gate dielectric layer (lower half of 116 – implied but not shown), wherein the first gate dielectric layer (lower half of 116) and the second gate dielectric layer (upper half of 116) are made of a same material [0029],
and wherein the gate electrode vertically overlaps the (horizontally spaced apart) 2-d material layers (204).
Kim teaches a semiconductor device (TFT) fig. 2 [0022] wherein the second gate dielectric layer (32) fig. 2 [0024] forms an interface (border of 31/32 shown in fig. 2) with the first gate dielectric layer (31) fig. 2 [0022-0026], wherein the first gate dielectric layer (31) and the second gate dielectric layer (32) are made of a same material (both made of silicon dioxide material) [0024].
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified the transistor structure of Lin in view of Lin-II such that it adopts dual-layer SiO2 gate dielectric structure [0022-0026] of Kim in order to prevent step-disconnection of the gate electrode without causing degradation of device characteristics [0033-0036], and further, to extend the gate dielectric over and into direct contact with the source/drain electrodes [0022-0026] in order to increase the amount of dielectric material and thereby isolation between the gate, source/drain electrodes, and underlying semiconductor material [0022-0026], as taught by Kim.
However, Lin in view of Lin-II and Kim does not explicitly disclose and wherein the gate electrode vertically overlaps the (horizontally spaced apart) 2-d material layers (204).
Kim-II teaches a semiconductor device [see fig. 17C, 0093] wherein the gate electrode (500) fig. 17C [0093] vertically overlaps the (horizontally spaced apart) 2-d material layers (incorporated into/under respective 300A/300B s/d electrodes by Lin in view of Lin-II) [0093].
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified the transistor device of Lin in view of Lin-II and Kim such that the gate electrode of the transistor is laterally extended to vertically overlap all layers of the 2-D transistor [0093] including the source/drain electrodes [0093] in order to increase the area covered by transistor components [0089-0093] such as the gate electrode [0093], as taught by Kim--II.
Regarding claim 9, Lin in view of Lin-II and Kim and Kim-II teaches the semiconductor device (200) fig. 11 [0048] of claim 8. Lin also teaches wherein the 2-D material semiconductor layer (106) fig. 11 [0048] (TMD film [0047-0048]) is made of transition metal dichalcogenide (TMD) [0047-0048].
Regarding claim 10, Lin in view of Lin-II and Kim and Kim-II teaches the semiconductor device (200) fig. 11 [0048] of claim 8. Lin also teaches wherein the gate electrode (118) fig. 11 [0046] is in contact with a top surface of the second gate dielectric layer (upper half of 116) (see also fig. 2 of Kim).
Regarding claim 11, Lin in view of Lin-II and Kim and Kim-II teaches the semiconductor device (200) fig. 11 [0048] of claim 8. Lin in view of Lin-II and Kim (with reference to Kim) also teaches wherein the (70nm) [0032] second gate dielectric layer (32) fig. 2 [0022-0026] is thicker than the (10nm) [0031] first gate dielectric layer (31) fig. 2 [0022-0026].
Regarding claim 12, Lin in view of Lin-II and Kim and Kim-II teaches the semiconductor device (200) fig. 11 [0048] of claim 8. Lin also teaches wherein a bottom surface of the gate electrode (118) fig. 11 [0046] is higher than a topmost end of the first gate dielectric layer (included in 116) fig. 11 [0029, 0046].
Claims 15-18 are rejected under 35 U.S.C. 103 as being unpatentable over Kim (U.S. PG Pub No US2019/0164754A1) (of record) in view of Lin (U.S. PG Pub No US2019/0378715A1) (of record) and Gao (CN Pub No CN-111969058-A) (of record) (see attached translation (of record) for line reference #’s).
Regarding claim 15, Kim teaches a semiconductor device [see fig. 17C, 0093], comprising:
a substrate (200) fig. 17C [0093];
a 2-D material semiconductor layer (210a) fig. 17C [0092-0094] over the substrate (200);
source/drain electrodes (300A/300B) fig. 17C [0093] covering opposite (left/right) sides of the 2-D material semiconductor layer (210a),
a first gate dielectric layer (400) fig. 17C [0093] in direct contact with the 2-D material semiconductor layer (210a) and the source/drain electrodes (300a/b), wherein opposite sidewalls of each of the source/drain electrodes (300a/b) are in (direct) contact with the first gate dielectric layer (400); and
a gate electrode (500) fig. 17C [0093] over the gate dielectric layer (400).
However, Kim does not explicitly disclose wherein each of the source/drain electrodes comprises a 2-D material semimetal layer and a metal over the 2-D material semimetal layer (composition undefined) [0093], wherein an entirety of the metal is spaced apart from the 2-d material semiconductor layer (210a),
wherein opposite sidewalls of the 2-D material semimetal layer of each of the source/drain electrodes (300a/b) are in contact with the first gate dielectric layer (400);
a second gate dielectric layer over the first gate dielectric layer (400), wherein the first gate dielectric layer (400) and the second gate dielectric layer are made of different materials; and
a gate electrode (500) over the second gate dielectric layer,
wherein the first gate dielectric layer (lower half of 116) has a stepped top surface and the second gate dielectric layer (upper half of 116) has an uppermost top surface that is coplanar and interfaces with the gate electrode (118).
Lin teaches a semiconductor device (800) fig. 8 [0057] wherein each of the source/drain electrodes (comprising right/left 710) fig. 8 [0057] comprises a 2-D material semimetal layer (right/left 720) fig. 8 [0057, 0045] and a metal (right/left 730) fig. 8 [0057, 0044] over the 2-D material semimetal layer (720),
wherein an entirety of the metal (730) is spaced apart from the 2-d material semiconductor layer (620) fig. 8 [0057, 0044],
wherein opposite sidewalls of the 2-D material semimetal layer (720s) of each of the source/drain electrodes (710) are in (thermal) contact with the first gate dielectric layer (812) [0057] (through highly conductive 740 material [0057]).
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified the transistor of Kim such that individual of the source and drain electrodes are paired with horizontally separated 2-D material layers [0044-0046] in order to improve the conductivity of the source/drain electrode stacks [0013-0014, 0044] and enhance crystalline properties of device materials [0047], as taught by Lin.
However, Kim in view of Lin still does not explicitly teach a second gate dielectric layer over the first gate dielectric layer (400), wherein the first gate dielectric layer (400) and the second gate dielectric layer are made of different materials; and
a gate electrode (500) over the second gate dielectric layer,
wherein the first gate dielectric layer (lower half of 116) has a stepped top surface and the second gate dielectric layer (upper half of 116) has an uppermost top surface that is coplanar and interfaces with the gate electrode (118).
Gao teaches a semiconductor device [see title, fig 1] comprising a second gate dielectric layer (8) fig. 1 [lines 317-327] over the first gate dielectric layer (7) fig. 1 [lines 317-327], wherein the first gate dielectric layer (7) and the second gate dielectric layer (8) are made of different (overall) materials (7 made of aluminum oxide while 8 is hafnium oxide [lines 317-320]).
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified the gate dielectric layer(s) of Kim in view of Lin to have been composed of the materials explicitly described by Gao [lines 317-327] in order to optimize their sizes and dielectric constants according to art recognized suitability, as evidenced by Gao [lines 317-327]. Moreover, it is evident to one of ordinary skill in the art that stretching the gate dielectrics over the source/drain electrodes would increase the isolation between the gate electrode and lower layers.
However, Kim in view of Lin still does not explicitly teach a second gate dielectric layer over the first gate dielectric layer (400), wherein the first gate dielectric layer (400) and the second gate dielectric layer are made of different materials; and
a gate electrode (500) over the second gate dielectric layer,
wherein the first gate dielectric layer (lower half of 116) has a stepped top surface and the second gate dielectric layer (upper half of 116) has an uppermost top surface that is coplanar and interfaces with the gate electrode (118).
Hiramatsu teaches a semiconductor device [see fig. 2, 0022] wherein the first gate dielectric layer (31) fig. 2 [0024] has a stepped top surface (stepped over channel layer 20) [0024] and the second gate dielectric layer (32) fig. 2 [0024] has an uppermost top surface that is coplanar and interfaces with the gate electrode (40) fig. 2 [0025].
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified the transistor structure of Lin in view of Lin-II and Gao such that it adopts dual-layer gate dielectric structure [0024-0025] of Hiramatsu in order to effectively form a stepped gate insulating layer [0018, 0020, 0024] capable of providing sufficient insulation between the gate electrode, channel, and source/drain electrodes [0024-0025] in the TFT, as taught by Hiramatsu.
Regarding claim 16, Kim in view of Lin, Gao, and Hiramatsu teaches the semiconductor device [see fig. 17C, 0093] of claim 15. However, Kim does not explicitly disclose wherein the second gate dielectric layer is thicker than the first gate dielectric layer (400) fig. 17C [0093].
Gao teaches a semiconductor device [see title, fig. 1] wherein the (upper) second gate dielectric layer (8) fig. 1 [lines 317-327] is thicker than the (lower) first gate dielectric layer (7) fig. 1 [lines 317-327].
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified the gate dielectric layer(s) of Kim to have the multilayer, multi-material structure [lines 317-327] of Gao with respective thicknesses explicitly described by Gao [lines 317-327] in order to optimize their sizes according to art recognized suitability, as evidenced by Gao [lines 317-327].
Regarding claim 17, Kim in view of Lin, Gao, and Hiramatsu teaches the semiconductor device [see fig. 17C, 0093] of claim 15. Kim also teaches wherein a bottom surface of the gate electrode (500) fig. 17C [0093] is higher than a topmost end of the first gate dielectric layer (400) fig. 17C [0093] and topmost ends of the source/drain electrodes (300 A/B) fig. 17C [0093].
Regarding claim 18, Kim in view of Lin, Gao, and Hiramatsu teaches the semiconductor device [see fig. 17C, 0093] of claim 15. However, Kim does not explicitly disclose wherein the second gate dielectric layer has a flat top surface profile spanning over the source/drain electrodes (300 a/b) fig. 17C [0093], while the first gate dielectric layer (400) fig. 17C [0093] has a stepped top surface profile.
Gao teaches a semiconductor device [see title, fig 1] wherein the (upper) second gate dielectric layer (8) fig. 1 [lines 317-327] has a flat top surface profile (middle portion) spanning over (inner half-portions of) the source/drain electrodes (comprising 5, 6) fig. 1 [lines 354-357], while the (lower) first gate dielectric layer (7) fig. 1 [lines 317-327] has a stepped top surface profile (near peripheral portion).
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified the gate dielectric layer(s) of Kim to have the multilayer, multi-material structure [lines 317-327] of Gao with respective thicknesses explicitly described by Gao [lines 317-327] in order to optimize their sizes according to art recognized suitability, as evidenced by Gao [lines 317-327].
Claims 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Kim (U.S. PG Pub No US2019/0164754A1) (of record) in view of Lin (U.S. PG Pub No US2019/0378715A1) (of record) and Gao (CN Pub No CN-111969058-A) (of record) (see attached translation (of record) for line reference #’s), as applied in claim 15 above, and further in view of Lin-II (U.S. PG Pub No US2020/0006541A1).
Regarding claim 19, Kim in view of Lin and Gao teaches the semiconductor device [see fig. 17C, 0093] of claim 15. However, Kim does not explicitly disclose further comprising 2-D material layers in contact with the opposite sides of the 2-D material semiconductor layer (210a) fig. 17C [0092-0094] and horizontally spaced apart from each other, wherein the source/drain electrodes (300A/300B) fig. 17C [0093] are over the 2-D material layers, respectively.
Lin-II teaches a semiconductor device (300) fig. 2H [0056] further comprising 2-D material layers (230(1), 230(2)) fig. 2H [0050-0054] in contact with the opposite sides of the 2-D material semiconductor layer (222) fig. 2H [0056] (MoS2 film [0056]) and horizontally spaced apart from each other, wherein the source/drain electrodes (comprising metal 240) fig. 2H [0048-0049, 0059] are over the 2-D material layers (230), respectively.
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified the transistor device of Kim to include the horizontally-spaced 2-D material layers of Lin intervening the source/drain metal and 2-D semiconductor layer [0051-0059] in order to desirably tune the conductivity properties of the source/drain electrodes [0009, 0045], as taught by Lin-II.
Regarding claim 20, Kim in view of Lin, Gao, and Lin-II teaches the semiconductor device [see fig. 17C, 0093] of claim 19. Kim view of Lin-II (with reference to Lin-II) also teaches wherein the 2-D material layers (230(1), 230(2)) fig. 2H [0050-0054 Lin] are made of graphene (“any 2-d material” different from the first [0037 Lin; [0001-0002, 0051] of Lin discloses graphene as a 2-D material).
Claim 21 is rejected under 35 U.S.C. 103 as being unpatentable over Lin (U.S. PG Pub No US2017/0345944A1) (of record) in view of Lin-II (U.S. PG Pub No US2019/0378715A1) (of record) and Hiramatsu (U.S. PG Pub No US2014/0346497A1) (of record), as applied in claim 1 above, and further in view of Tanaka (U.S. PG Pub No US2015/0303217A1) (of record).
Regarding claim 21, Lin in view of Lin-II and Hiramatsu teaches the semiconductor device (200) fig. 11 [0048] of claim 1. However, Lin does not explicitly disclose wherein the 2-D material semiconductor layer (204) fig. 11 [0048] (TMD film [0048]) has a triangular top profile.
Tanaka teaches a semiconductor device (32) fig. 24C [0454] wherein the 2-D material semiconductor layer (represented by channel 114) fig. 24C [0457] has a triangular top (top = peripheral surface) profile [0457].
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified the transistor of Lin such that the channel layer is formed to have a triangular profile [0454-0457] in order to improve relative angles with adjacent insulator layers [0458] in a manner that boosts current density and on-state current [0458] of the transistor, as taught by Tanaka.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1, 8, and 15 have been considered but are moot because they fail to specifically point out the supposed errors of the rejection of record with respect to the claim amendments – particularly with respect to the express teachings of secondary reference Hiramatsu (U.S. PG Pub No US2014/0346497A1) (of record) and the claim amendment(s) for independent claims 1 and 15. Therefore, the rejection(s) presented above are considered as a sufficient response-to-arguments for Applicant’s Claims and associated Remarks submitted 10/23/2025.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Remaining references made of record on the PTO-892 form (of record) disclose transistors with at least some of the newly-claimed features.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SEAN AYERS WINTERS whose telephone number is (571)270-3308. The examiner can normally be reached Monday - Friday 10:30 am - 7:00 pm (EST).
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/SEAN AYERS WINTERS/Examiner, Art Unit 2892 12/20/2025
/ERIC W JONES/Primary Examiner, Art Unit 2892
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