DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Election/Restrictions
Applicant's election without traverse of Species I directed to Fig. 1-9 (claims 1-2, 4-6 and 9-17) in the reply filed on March 18th, 2026 is acknowledged.
Claims 3, and 7-8 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Species, there being no allowable generic or linking claim.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 12-16 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
Claim 12 recites the limitation “the first wire” in line 2. There is insufficient antecedent basis for this limitation in the claim.
Claim 13 recites the limitation “the first portion of the first wire” in lines 7-8. There is insufficient antecedent basis for this limitation in the claim.
Claim 14 recites the limitation “wherein a distance from the first electrode to a portion of the covering portion that is the farthest from the first electrode is larger than a distance from the first electrode to a portion of the first portion that is the farthest from the first electrode”. It is unclear to the examiner how can the same distance is being larger than each other.
Claim 16 recites the limitation “the first wire includes a second portion” in lines 2. It is unclear to the examiner how can the first wire has the second portion without having the first portion.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
a. Determining the scope and contents of the prior art.
b. Ascertaining the differences between the prior art and the claims at issue.
c. Resolving the level of ordinary skill in the pertinent art.
d. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-2, 4-5, 9, 12 and 13-17 are rejected under 35 U.S.C. 103 as being unpatentable over ITO (Pub. No.: US 2019/0043827 A1) in view of MATSUI et al. (Pub. No.: US 2021/0217724 A1), hereinafter as Matsui.
Regarding claim 1, ITO discloses a semiconductor device in Fig. 9 including: a semiconductor element (semiconductor device 2/front-side electrode 22) that includes an element body (semiconductor device 2) containing a semiconductor and a first electrode (front-side electrode 22) disposed on the element body (see [0033-0036]); a sealing material (second sealing member 5 made of silicone gel) that covers the semiconductor element (see [0048]); and a covering portion (first sealing member 4) interposed between the first electrode and the sealing material, the covering portion containing a material (made of Tin alloy) having a higher thermal conductivity than the sealing material (metal alloy has higher thermal conductivity than silicone gel) (see [0044-0045]), wherein the first electrode includes a groove portion (recess 23) held in contact with the covering portion (see [0068]).
ITO fails to disclose the sealing material is sealing resin.
Matsui discloses a semiconductor device in Fig. 2 comprising a sealing resin (sealing member 60 made of silicone resin) covers a semiconductor element (semiconductor element 20) (see [0125-0126]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the material of the sealing material of ITO to be made from resin as same as the material of Matsui’s semiconductor device because the disclosure of Matsui showing that either silicone gel or silicone resin can be effectively used as sealing material for protecting the semiconductor chip and choosing silicone resin can be manufacturing choice.
Regarding claim 2, ITO and Matsui disclose the semiconductor device according to claim 1, wherein the first electrode includes a first layer (front-side layer 22 has the layer as first layer), and the groove portion is a portion recessed in the first layer (see Fig. 9).
Regarding claim 4, ITO and Matsui disclose the semiconductor device according to claim 1, wherein the groove portion includes an outer peripheral portion (right recess 23) arranged along an outer circumference of the first electrode (outer edge of front-side electrode 22) (see Fig. 9).
Regarding claim 5, ITO and Matsui disclose the semiconductor device according to claim 4, wherein the groove portion includes an inner portion (left recess 23) disposed inward of the outer peripheral portion (see Fig. 9).
Regarding claim 9, ITO and Matsui disclose the semiconductor device according to claim 1, wherein the covering portion contains a metal (see [0045])
Regarding claim 12, ITO and Matsui disclose the semiconductor device according to claim 9, wherein the first wire (bonding wire 3) contains Al (see [0037]).
Regarding claim 13, ITO and Matsui disclose the semiconductor device according to claim 1, further comprising a first wire (bonding wire 3) bonded to the first electrode (see [0037]), wherein the first electrode includes a first portion (left half of front-side electrode 23) extending from an inner part of the first electrode toward an outer part of the first electrode as viewed in a thickness direction of the semiconductor element (see Figs. 9-10), and the covering portion is in contact with the first portion of the first wire (see Fig. 9).
Regarding claim 14, ITO and Matsui disclose the semiconductor device according to claim 13, wherein a distance from the first electrode to a portion of the covering portion that is the farthest from the first electrode is larger than a distance from the first electrode to a portion of the first portion that is the farthest from the first electrode (comparing the same limitation and this is being rejected by 112 above) (see Fig. 9).
Regarding claim 15, ITO and Matsui disclose the semiconductor device according to claim 14, wherein the covering portion covers at least a part of the first portion from a location opposite to the semiconductor element in the thickness direction (see Fig. 9).
Regarding claim 16, ITO and Matsui disclose the semiconductor device according to claim 13, wherein the first wire includes a second portion (curved upper portion of the bonding wire 3) connected to the first portion at a side opposite to the first electrode, the second portion being upright along the thickness direction and extending away from the semiconductor element (see Fig. 9).
Regarding claim 17, ITO and Matsui disclose the semiconductor device according to claim 13, wherein the first wire contains Cu (see [0037]).
Claims 10-11 are rejected under 35 U.S.C. 103 as being unpatentable over ITO (Pub. No.: US 2019/0043827 A1) in view of MATSUI et al. (Pub. No.: US 2021/0217724 A1), hereinafter as Matsui, as applied to claim 9 and further in view of HINO (Pub. No.: US 2019/0122998 A1).
Regarding claim 10, ITO and Matsui disclose the semiconductor device according to claim 9, but fails to disclose wherein the covering portion contain Ag or Cu.
HINO discloses a semiconductor device comprising a covering portion (bonding material 8) contain sintered Ag or sintered Cu (see Fig. 1 and [0059]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the covering portion of ITO to be made from sintered Ag or sintered Cu as same as the material of the semiconductor device of HINO because the disclose of HINO showing that sintered Ag or sintered Cu can be effectively used as substitute material for Tin (Sn) to form the covering portion.
Regarding claim 11, ITO and Matsui disclose the semiconductor device according to claim 10, but fails to disclose wherein the covering portion contain sintered Ag or sintered Cu.
HINO discloses a semiconductor device comprising a covering portion (bonding material 8) contain sintered Ag or sintered Cu (see Fig. 1 and [0059]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the covering portion of ITO to be made from sintered Ag or sintered Cu as same as the material of the semiconductor device of HINO because the disclose of HINO showing that sintered Ag or sintered Cu can be effectively used as substitute material for Tin (Sn) to form the covering portion.
Allowable Subject Matter
Claim 6 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is an examiner's statement of reasons for the indication of allowable subject matter: The cited art, whether taken singularly or in combination, especially when all limitations are considered within the claimed specific combination, fails to disclose or suggest the claimed invention having: wherein the inner portion is latticed-shaped as recited in claim 6.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CUONG B NGUYEN whose telephone number is (571)270-1509 (Email: CuongB.Nguyen@uspto.gov). The examiner can normally be reached Monday-Friday, 8:30 AM-5:00 PM Eastern Standard Time.
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/CUONG B NGUYEN/Primary Examiner, Art Unit 2818
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