Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Title
In the remarks filed on 05/06/2026, the applicant accepted the previously suggested title as below:
“SEMICONDUCTOR DEVICE INCLUDING A SCHOTTKY BARRIER DIODE AND METHOD FOR MANUFACTURING THE SEMICONDUCTOR DEVICE”
DETAILED ACTION
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1, 7-10 and 12-15 are rejected under 35 U.S.C. 103 as being unpatentable over Ichikawa (Pub. No. US 2019/0109005 A1) in view of Sharma et al. (Pub. No. US 2021/0384419 A1, herein Sharma).
Regarding claim 1, Ichikawa discloses semiconductor device comprising: a semiconductor layer 42 (Ichikawa: Fig. 1 and paragraph [0038]); and a Schottky electrode 34 that is formed at a first surface of the semiconductor layer and that forms a Schottky junction portion between the semiconductor layer and the Schottky electrode (Ichikawa: Fig. 1 and paragraph [0040]), wherein the Schottky electrode has a first portion that is selectively formed near the first surface of the semiconductor layer in a thickness direction of the Schottky electrode and that is made of Mo containing oxygen (Ichikawa: Figs. 1, 9 and paragraphs [0011]-[0012], [0034]-[0035]).
Ichikawa introduces Ti for electrode 32 but does not specifically state the metal used for the Schottky electrode is Ti containing oxygen, and when an analysis is made in a first direction from the Schottky electrode toward the semiconductor layer according to a predetermined quantitative-analysis method, an oxygen concentration profile corresponding to an inside of the first portion has a peak at a position closer to a boundary portion between the first portion and the semiconductor layer than a center position of the first portion in the first direction.
However, to provide support for the assertion made in the previous office action with regard to the rejection of claim 4’s limitations (now added to claim 1), Sharma in paragraph [0038] says “when a first voltage, e.g., set operating voltage, is applied to the storage cell 212 through the first electrode 207 and the second electrode 201, oxygen ions may move from the resistive switching material layer 203 to the semiconductor layer 205, which is the oxygen exchange layer (OEL) of the storage cell 212. As oxygen ions are moved to the semiconductor layer 205 an oxygen ion concentration may be formed at the interface between the semiconductor layer 205 and the first electrode 207. As the oxygen ion concentration increases, a Schottky barrier may be formed between the semiconductor layer 205 and the first electrode 207, increasing the resistance value of the semiconductor layer 205. Accordingly, when resistance of the semiconductor layer 205 becomes higher, the resistance value of the storage cell 212 also becomes higher resistance. Therefore, the resistance of the storage cell 212 goes through a set process to switch from a first resistance value to a second resistance value. Hence, it may be considered that a first bit of data, e.g., “1” or “0”, is written to the storage cell 212.”
Furthermore, a Schottky electrode is commonly evaluated using predetermined quantitative analysis methods to extract parameters such as barrier height, ideality factor, and series resistance. These analyses are typically based on standard semiconductor equations (I-V curve fitting, C-V analysis, Richardson Plot Analysis, Cheung’s method for series resistance extraction, Norde Method) derived from thermionic emission theory and measured I-V or C-V characteristics. Because the governing equations and extraction techniques are well established, a skilled person can routinely calculate the electrode characteristics from measured data. Therefore, the calculations are often considered obvious and straightforward in semiconductor device analysis.
Therefore, given the teachings of Sharma, a person having ordinary skill in the art before the effective filing date of the claimed invention would have readily recognized the desirability and advantages of modifying Ichikawa in view of Sharma by employing the configuration of Sharma.
Regarding claim 7, Ichikawa in view of Sharma teaches the semiconductor device according to Claim 1, wherein the semiconductor layer does not contain oxygen near the first surface in the Schottky junction portion (Ichikawa: Figs. 1, 9 and paragraphs [0034]-[0040] and Sharma: paragraph [0038]).
Regarding claim 8, Ichikawa in view of Sharma teaches the semiconductor device according to Claim 1, further comprising a front surface electrode 30 that is formed on the Schottky electrode and that is made of an Al alloy or Al (Ichikawa: Figs. 1, 9 and paragraph [0040]).
Regarding claim 9, Ichikawa in view of Sharma teaches the semiconductor device according to Claim 8, wherein the Al alloy includes at least one among an AlCu alloy, an AlSi alloy, and an AlSiCu alloy (Ichikawa: Figs. 1, 9 and paragraph [0040]). See In re Leshin, 125 USPQ 416 (CCPA 1960) where the court stated that a selection of a material on the basis of suitability for intended use of an apparatus would be entirely obvious.
Regarding claim 10, Ichikawa in view of Sharma teaches the semiconductor device according to Claim 1, wherein the semiconductor layer includes a first conductivity type semiconductor layer 42, and the semiconductor device further comprises a second conductivity type impurity region 38 that is selectively formed at the first surface of the semiconductor layer so as to be contiguous to the Schottky electrode and that makes a p-n junction between the semiconductor layer and the second conductivity type impurity region (Ichikawa: Figs. 1, 9 and paragraph [0046]).
Regarding claim 12, Ichikawa in view of Sharma teaches the semiconductor device according to Claim 10, wherein the first conductivity type is an n-type, and the second conductivity type is a p-type (Ichikawa: Figs. 1, 9 and paragraph [0046]).
Regarding claim 13, Ichikawa in view of Sharma teaches the semiconductor device according to Claim 1, wherein the semiconductor layer includes a SiC semiconductor layer (Ichikawa: Figs. 1, 9 and paragraph [0007]).
Regarding claim 14, Ichikawa discloses a method for manufacturing a semiconductor device, the method comprising: a step of introducing oxygen into a first surface of the semiconductor layer 42 having the first surface; a step of forming a Schottky electrode 34 having a first portion made of a metal that is contiguous to the first surface of the semiconductor layer by depositing the metal on the first surface of the semiconductor layer; and a step of diffusing the oxygen introduced into the semiconductor layer into the first portion of the Schottky electrode by annealing treatment (Ichikawa: Figs. 1, 9 and paragraphs [0011]-[0012], [0034]-[0035]).
Ichikawa introduces Ti for electrode 32 but does not specifically state the metal used for the Schottky electrode is Ti containing oxygen, and when an analysis is made in a first direction from the Schottky electrode toward the semiconductor layer according to a predetermined quantitative-analysis method, an oxygen concentration profile corresponding to an inside of the first portion has a peak at a position closer to a boundary portion between the first portion and the semiconductor layer than a center position of the first portion in the first direction.
However, to provide support for the assertion made in the previous office action with regard to the rejection of claim 4’s limitations (now added to claim 1), Sharma in paragraph [0038] says “when a first voltage, e.g., set operating voltage, is applied to the storage cell 212 through the first electrode 207 and the second electrode 201, oxygen ions may move from the resistive switching material layer 203 to the semiconductor layer 205, which is the oxygen exchange layer (OEL) of the storage cell 212. As oxygen ions are moved to the semiconductor layer 205 an oxygen ion concentration may be formed at the interface between the semiconductor layer 205 and the first electrode 207. As the oxygen ion concentration increases, a Schottky barrier may be formed between the semiconductor layer 205 and the first electrode 207, increasing the resistance value of the semiconductor layer 205. Accordingly, when resistance of the semiconductor layer 205 becomes higher, the resistance value of the storage cell 212 also becomes higher resistance. Therefore, the resistance of the storage cell 212 goes through a set process to switch from a first resistance value to a second resistance value. Hence, it may be considered that a first bit of data, e.g., “1” or “0”, is written to the storage cell 212.”
Furthermore, a Schottky electrode is commonly evaluated using predetermined quantitative analysis methods to extract parameters such as barrier height, ideality factor, and series resistance. These analyses are typically based on standard semiconductor equations (I-V curve fitting, C-V analysis, Richardson Plot Analysis, Cheung’s method for series resistance extraction, Norde Method) derived from thermionic emission theory and measured I-V or C-V characteristics. Because the governing equations and extraction techniques are well established, a skilled person can routinely calculate the electrode characteristics from measured data. Therefore, the calculations are often considered obvious and straightforward in semiconductor device analysis.
Therefore, given the teachings of Sharma, a person having ordinary skill in the art before the effective filing date of the claimed invention would have readily recognized the desirability and advantages of modifying Ichikawa in view of Sharma by employing the configuration of Sharma.
Regarding claim 15, the use of the particular type of cleaning and washing process by Applicant is considered to be nothing more than the use of one of numerous and well-known alternate types of cleaning process that a person having ordinary skill in the art would have been able to provide using routine experimentation; as the grown oxide consumes surface contaminations and defects, which are then removed when the oxide is stripped, whereas the liquid washing is a simple, low cost, scalable and compatible with a wide range of materials and process flows. Therefore, a person having ordinary skill in the art before the effective filing date of the claimed invention would have readily recognized the desirability and advantages of washing the first surface of the semiconductor layer by means of a chemical liquid, wherein the step of introducing oxygen includes a step of introducing oxygen into the semiconductor layer by irradiating oxygen plasma toward the first surface of the semiconductor layer washed by the chemical liquid.
Claims 2 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Ichikawa in view of Sharma, as applied above, and further in view of Emiko (JP 2002217210 A).
Regarding claim 2, the previous combination is silent about the Schottky electrode having a second portion that is formed on the first portion and that is made of Ti and N.
However, in the same field of endeavor, Emiko states “a method of manufacturing a semiconductor device, comprising: forming a first layer containing titanium and nitrogen or oxygen or both on the semiconductor region to form the Schottky barrier electrode… A first layer forming a Schottky barrier at an interface with the semiconductor region; and a second layer stacked on an upper surface of the first layer, wherein the first layer is nitrogen or oxygen or nitrogen and oxygen preferably, the second layer is made of a metal material having a characteristic of making low-resistance contact with the semiconductor region...a first layer forming a Schottky barrier at an interface with the semiconductor region; and a second layer stacked on an upper surface of the first layer, wherein the first layer includes titanium and nitrogen or oxygen or containing both of these, and having a titanium content of 50 to 90% by weight”.
Therefore, given the teachings of Emiko, a person having ordinary skill in the art before the effective filing date of the claimed invention would have readily recognized the desirability and advantages of modifying the previous combination in view of Emiko by employing the Schottky electrode having a second portion that is formed on the first portion and that is made of Ti and N.
Regarding claim 16, Ichikawa in view of Sharma and further in view of Emiko teaches the method for manufacturing a semiconductor device according to Claim 14, wherein the step of forming a Schottky electrode includes a step of forming a second portion made of Ti and N on the first portion by additionally depositing Ti in an N2 atmosphere after the first portion is formed (Ichikawa: Figs. 1, 9 and paragraph [0007]).
Allowable Subject Matter
Claims 3 and 5-6 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim 11 is allowed.
The following is a statement of reasons for the indication of allowable subject matter:
With respect to claim 3, the prior art of record alone or in combination do not teach or fairly suggest, in combination with other elements of the claims, wherein an oxygen concentration near the Schottky junction portion is higher than both an oxygen concentration in the vicinity of an interface between the first portion and the second portion and an average oxygen concentration of the semiconductor layer.
With respect to claim 5, the prior art of record alone or in combination do not teach or fairly suggest, in combination with other elements of the claims, wherein a concentration at the peak of the oxygen concentration profile is not less than 2.0 atm% and not more than 10.0 atm%.
With respect to claim 6, the prior art of record alone or in combination do not teach or fairly suggest, in combination with other elements of the claims, further comprising an insulation layer that is formed at the first surface of the semiconductor layer and that has an opening from which the first surface is partially exposed, wherein the Schottky electrode includes a first covering portion that covers the first surface of the semiconductor layer in the opening of the insulation layer and a second covering portion that is formed outside the opening of the insulation layer and that covers the insulation layer, and the first portion selectively contains oxygen in the first covering portion of the Schottky electrode, and does not contain oxygen in the second covering portion.
With respect to claim 11, the prior art of record alone or in combination do not teach or fairly suggest, in combination with other elements of the claims, further comprising a lattice defect region that is selectively formed at the first surface of the semiconductor layer so as to be contiguous to the Schottky electrode and that has lattice defects more than the semiconductor layer, and the impurity region includes a first region formed inside the lattice defect region so as to be contiguous to the lattice defect region.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Response to Arguments
Applicant’s arguments with respect to claims 1-2, 7-10 and 12-16 have been fully considered, but are found to be moot in view of the new grounds of rejection.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MALIHEH MALEK whose telephone number is (571)270-1874. The examiner can normally be reached M/T/W/R/F, 8:30-5.
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May 22, 2026
/MALIHEH MALEK/Primary Examiner, Art Unit 2813
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