Prosecution Insights
Last updated: April 19, 2026
Application No. 18/481,292

Semiconductor Package Assembly

Non-Final OA §102§112
Filed
Oct 05, 2023
Examiner
MILLER, JAMI VALENTINE
Art Unit
2818
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Nexperia B V
OA Round
1 (Non-Final)
95%
Grant Probability
Favorable
1-2
OA Rounds
2y 2m
To Grant
99%
With Interview

Examiner Intelligence

Grants 95% — above average
95%
Career Allow Rate
1011 granted / 1067 resolved
+26.8% vs TC avg
Minimal +4% lift
Without
With
+3.9%
Interview Lift
resolved cases with interview
Typical timeline
2y 2m
Avg Prosecution
23 currently pending
Career history
1090
Total Applications
across all art units

Statute-Specific Performance

§101
0.3%
-39.7% vs TC avg
§103
27.2%
-12.8% vs TC avg
§102
45.6%
+5.6% vs TC avg
§112
24.4%
-15.6% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1067 resolved cases

Office Action

§102 §112
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Status of Claims Claims 1-19 are pending in this application. Foreign Priority Receipt is acknowledged of certified copies of papers submitted under 35 U.S.C. 119(a)-(d), which papers have been placed of record in the file. Information Disclosure Statement Acknowledgment is made that the information disclosure statement has been received and considered by the examiner. If the applicant is aware of any prior art or any other co-pending applications not already of record, he/she is reminded of his/her duty under 37 CFR 1.56 to disclose the same. Drawings There are no objections or rejections to the drawings. Specification The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. Claims 1-19 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention. Claim 1 recites the limitation “a lead frame having a first lead frame side and a second lead frame side opposite to the first lead frame side; a semiconductor die structure having a first die side and a second die side opposite to the first die side, wherein the semiconductor die structure is mounted with its second die side on the first lead frame side of the lead frame, resulting in a first conductive connection; at least one bond element being connected to the first die side of the semiconductor die structure, resulting in at least a one further conductive connection; wherein the molding resin case encapsulates at least the semiconductor die structure, and wherein the lead frame and a first element part of the at least one bond element connected to the semiconductor die structure, leaves at least the second side of the lead frame and the other element part of the at least one bond element partly exposed”. It is unclear what is meant by the second side of the lead frame. One reasonable interpretation is that the second side of the lead frame is the same as the second lead frame side opposite to the first lead frame side; or if the second side of the lead frame is different than the second lead frame side opposite to the first lead frame side. The limitation does not have well defined boundaries. One of ordinary skill in the relevant art would not know what structures/steps are covered by the limitation. For these reasons, the claim is indefinite. Claim 18 recites the limitation “wherein the angle is between 45°-90°”. It is unclear what is meant by wherein the angle is between 45°-90 because there is no frame of reference defining the angle. The limitation does not have well defined boundaries. One of ordinary skill in the relevant art would not know what structures/steps are covered by the limitation. For these reasons, the claim is indefinite. Claims 2-19 depend from rejected claim 1, include all limitations of claim 1 and therefore are rejected for the same reason. Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of pre-AIA 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention. (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claims 1-4, 7, 9-10, 13-14, 17-18 are rejected under pre-AIA 35 U.S.C. 102(a)(1) as being anticipated by Matsugi et al. (US Patent Application Publication No 2016/354868) hereinafter referred to as Matsugi. Per Claim 1 Matsugi discloses a semiconductor package assembly device, consisting of a semiconductor package and a molding resin case (5) (see figure 2 and [0061], the semiconductor package comprising: a lead frame (pad 2, left side) having a first lead frame side (top) and a second lead frame side (bottom) opposite to the first lead frame side; a semiconductor die structure (3) having a first die side (top) and a second die side (bottom) opposite to the first die side, wherein the semiconductor die structure is mounted with its second die side (bottom) on the first lead frame side (top) of the lead frame, resulting in a first conductive connection (1); (see figure 2) at least one bond element (lead 2, right side, which has five portions, labeled A-E, below) being connected to the first die side (top) of the semiconductor die structure (3), resulting in at least a one further conductive connection (4) (as shown in figure 2); wherein the molding resin case (5) encapsulates at least the semiconductor die structure (3), and wherein the lead frame (pad 2, left side) and a first element part (2A-B) of the at least one bond element (lead 2 on the right side) connected to the semiconductor die structure (3), leaves at least the second side of the lead frame (pad 2, left side. bottom) and the other element part (2C-E) of the at least one bond element (2, right) partly exposed (not covered by resin, see figure 2); The examiner notes that the term "connected" includes "directly connected" (no intermediate materials, elements or space disposed therebetween) and "indirectly connected " (intermediate materials, elements or space disposed therebetween) wherein the at least one bond element (lead 2, right side, which has five portions, labeled A-E, below) is provided with electric field modulation structures (2A-C), and wherein the electric field modulation structures are formed as a shielding plate (2C-D) mounted to the first element part (2A-B) of the at least one bond element (lead 2, right side), and the shielding plate extends (2C-D) from the first element part (2A-B) of the at least one bond element (downwards) towards the lead frame (pad 2, left side). (The Examiner notes that the lead structure of Matsugi figure 2 is identical to the embodiment disclosed in figure 4a of the present application) PNG media_image1.png 419 786 media_image1.png Greyscale Additionally, claim 1 recites the performance properties of the device (i.e. structured to alter an electric field created between the first conductive connection (1) and the at least further conductive connection (4) during operation of the semiconductor package assembly). This functional limitation does not distinguish the claimed device over the prior art, since it appears that this limitation can be performed by the prior art structure of Matsugi. While features of an apparatus may be recited either structurally or functionally, claims directed to an apparatus must be distinguished from the prior art in terms of structure rather than function. In re Schreiber, 128 F.3d 1473, 1477-78, 44 USPQ2d 1429,1431-32 (Fed. Cir. 1997) See MPEP 2114. Per Claim 2 Matsugi discloses the device of claim 1, including the electric field modulation structures structures (2A-C). Additionally, claim 2 recites the performance properties of the device (i.e. where the electric field modulation structures are structured to limit or reduce the electric field outside the molding resin case). This functional limitation does not distinguish the claimed device over the prior art, since it appears that this limitation can be performed by the prior art structure of Matsugi. While features of an apparatus may be recited either structurally or functionally, claims directed to an apparatus must be distinguished from the prior art in terms of structure rather than function. In re Schreiber, 128 F.3d 1473, 1477-78, 44 USPQ2d 1429,1431-32 (Fed. Cir. 1997) See MPEP 2114. Per Claim 3 Matsugi discloses the device of claim 1, including where the electric field modulation structures (2A-C) are encapsulated by the molding resin case (5). Per Claim 4 Matsugi discloses the device of claim 1, including where the shielding plate (2C) extends at an angle from the first element part (2A-B) of the at least one bond element towards either the exposed other element part (2D-E) of the bond element or towards the semiconductor die structure (3). (see figure 2) Per Claim 7 Matsugi discloses the device of claim 1, including where the first part (top) of the at least one bond element (lead 2, right side) is provided with a bond clip or a bond wire (4) connected with the first die side (top) of the semiconductor die structure (3) Per Claim 9 Matsugi discloses the device of claim 2, including where the electric field modulation structures (2A-C) are encapsulated by the molding resin case (5). Per Claim 10 Matsugi discloses the device of claim 2, including where the shielding plate (2C) extends at an angle from the first element part (2A-B) of the at least one bond element towards either the exposed other element part (2D-E) of the bond element or towards the semiconductor die structure (3). (see figure 2) Per Claim 13 Matsugi discloses the device of claim 2, including where the first part (top) of the at least one bond element (lead 2, right side) is provided with a bond clip or a bond wire (4) connected with the first die side (top) of the semiconductor die structure (3) Per Claim 14 Matsugi discloses the device of claim 3, including where the shielding plate (2C) extends at an angle from the first element part (2A-B) of the at least one bond element towards either the exposed other element part (2D-E) of the bond element or towards the semiconductor die structure (3). (see figure 2) Per Claim 17 Matsugi discloses the device of claim 3, including where the first part (top) of the at least one bond element (lead 2, right side) is provided with a bond clip or a bond wire (4) connected with the first die side (top) of the semiconductor die structure (3) Per Claim 18 Matsugi discloses the device of claim 4, including where the angle is between 45°-90°. (as shown in figure 2) Allowable Subject Matter Claims 5-6, 8, 11-12, 15-16 and 19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Cited Prior Art The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Applicants are directed to consider additional pertinent prior art included on the Notice of References Cited (PTOL 892) attached herewith. The Examiner has pointed out particular references contained in the prior art of record within the body of this action for the convenience of the Applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to JAMI VALENTINE MILLER whose telephone number is (571)272-9786. The examiner can normally be reached on Monday-Thursday 7am-5pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eva Montalvo can be reached on (571) 270-3829. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /Jami Valentine Miller/Primary Examiner, Art Unit 2818
Read full office action

Prosecution Timeline

Oct 05, 2023
Application Filed
Dec 24, 2025
Non-Final Rejection — §102, §112 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
95%
Grant Probability
99%
With Interview (+3.9%)
2y 2m
Median Time to Grant
Low
PTA Risk
Based on 1067 resolved cases by this examiner. Grant probability derived from career allow rate.

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