DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1, 2 & 4-11 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites “a substrate”, “a pad on the substrate”, “a solder resist layer on the substrate” and “… regardless of a distance from the substrate”. It is unclear what particular structural feature (e.g. in Applicant’s Fig. 1-3) refer to the substrate. The pad 130 is on the protection layer 120 and solder resist layer 140 and said limitation raises confusion in terms of positioning of the claim structural features. It appears that the claim is conflating the interconnection layer 110 with the substrate as the claim features are in relation to the interconnection layer. The drawing refers to the entire structure as the substrate 100 which further adds to the ambiguity. Correction/clarification is required.
Claims 2 & 4-11 are rejected for being dependent on claim 1.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
As best understood, claims 1-2, 4 & 6-9 are rejected under 35 U.S.C. 103 as being unpatentable over Darnon et al (US Pub. 2011/0115094) in view of JUNG et al. (KR-10-2008-0020365 – cited in the IDS filed on October 10, 2023).
Regarding claim 1, Darnon teaches a semiconductor device, comprising:
a substrate 12;
an interconnection pattern in the substrate 12 (Para [0033]);
a pad 26 on the substrate 12 and connected to the interconnection pattern (Para [0033] and Fig. 6); and
a solder resist layer 18’’ on the substrate 12, the solder resist layer having an opening exposing the pad 26,
a top surface of the pad including
a center region (center of pad 26, Fig. 6); and
a peripheral region surrounding the center region along an entire circumference of the pad (see Fig. 6 below),
and
a first width of the pad being constant regardless of a distance from the substrate.
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Darnon is silent on the center region of the top surface of the pad at a level different from the peripheral region of the top surface of the pad. However, JUNG teaches wherein a center region of a top surface of a pad 130 is at a level different from the peripheral region of the top surface of the pad 130. This presents the advantage of accommodating a solder ball within the center region of the pad in the subsequent stages. Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to modify the invention of Darnon with the pad structure, as taught by JUNG, so as to obtain an improved pad/contact structure.
Regarding claim 2, the combination of Darnon and JUNG teaches the semiconductor device of claim 1, wherein the center region of the top surface of the pad is at a level lower than the peripheral region of the top surface of the pad, and the center region comprises a concave surface that is recessed from the peripheral region (Darnon’s Fig. 6 and JUNG’s Fig. 2).
Regarding claim 4, the combination of Darnon and JUNG teaches the semiconductor device of claim 1, wherein the center region comprises a flat surface that is stepped with the peripheral region (JUNG’s Fig. 2).
Regarding claim 6, the combination of Darnon and JUNG teaches the semiconductor device of claim 1, wherein a level difference between the center and peripheral region is 10% to 50% of a thickness of the pad (see JUNG’s Fig. 2). Notwithstanding, it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working ranges involves only routine skill in the art. In re Aller, 105 USPQ 233. Furthermore, it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art. In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980).
Regarding claim 7, the combination of Darnon and JUNG teaches the semiconductor device of claim 6, wherein the level difference between the center and peripheral region ranges from 3 um to 10 um (JUNG teaches a height of about 40 um for the second bump 130 and it is plausible to read that the level difference between the center and the peripheral regions are in the ranges of 3um to 10 um, see Fig. 3b and associated text). Notwithstanding, it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working ranges involves only routine skill in the art. In re Aller, 105 USPQ 233. Furthermore, it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art. In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980).
Regarding claim 8, the combination of Darnon and JUNG teaches the semiconductor device of claim 1, wherein a width of the center region is 30% to 70% of a width of the pad (see JUNG’s Fig. 2). Notwithstanding, it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working ranges involves only routine skill in the art. In re Aller, 105 USPQ 233. Furthermore, it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art. In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980).
Regarding claim 9, the combination of Darnon and JUNG teaches the semiconductor device of claim 8, wherein the width of the center region ranges from 30 um to 50 um (JUNG teaches a height of about 40 um – 60 um for the second bump 130 and in light of said dimension, it is plausible to read that the width of the center region ranges from 30 um to 50 um, see Fig. 3b and associated text). Notwithstanding, it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working ranges involves only routine skill in the art. In re Aller, 105 USPQ 233. Furthermore, it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art. In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980).
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Darnon and JUNG as applied to claim 1 above, and further in view of Li et al. (US Pub. 2010/0164116).
Regarding claim 5, the combination of Darnon and JUNG is silent on the semiconductor device of claim 1, wherein the center region has a circular, tetragonal, polygonal, or cross shape, when viewed in a plan view. However, Li teaches a pad structure with that can comprise a circular, tetragonal, or polygonal, when viewed in a plan view (Para 0058]). This presents the advantage of providing a variety different shapes for the pad structure to optimize scaling. Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to modify the invention of Darnon & JUNG with the pad shapes, as taught by Li, so as to obtain an optimize scaling.
Claims 10-11 are rejected under 35 U.S.C. 103 as being unpatentable over Darnon and Jung as applied to claim 1 above, and further in view of KIM et al. (US Pub. 2016/0007459).
Regarding claim 10, the combination of Darnon and JUNG is silent on the semiconductor device of claim 1, wherein the solder resist layer is spaced apart from a pad. However, KIM teaches a semiconductor device, wherein a solder resist layer 34 is spaced apart from a pad 20 (see Fig. 2 & Fig. 15). This has the advantage of allowing for an improved contact structure to a semiconductor chip. Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to modify the invention of Darnon and JUNG with the pad structure, as taught by KIM, so as to obtain an improved contact structure.
Regarding claim 11, while the combination of Darnon and JUNG teaches the semiconductor device of claim 1, further comprising: a solder portion 140, wherein the solder portion 140 is in contact with an entirety of the center region (see JUNG’s Fig. 2); however, the combination of Darnon and JUNG is silent on a semiconductor chip having a bottom surface, on which a chip pad is provided. However, KIM teaches in Fig. 15 wherein a semiconductor chip 200 having a bottom surface, on which a chip pad 222 is provided. This has the advantage of providing an improved electrical/signal pathways between a lower and upper semiconductor structures. Once incorporated into Darnon and JUNG’s device, the solder portion 140 of JUNG or solder portion 224 of KIM would be positioned between the chip pad 222 and the pad 26/130 (Darnon’s Fig. 6 and JUNG’s Fig. 2) to directly connect the chip pad 222 to the pad (Darnon’s Fig. 6, JUNG’s Fig. 2 and KIM’s Fig. 15). Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to modify the invention of Darnon and JUNG with the semiconductor chip 200 and associate chip pad, as taught by KIM, so as to obtain an improved contact structure between an upper and lower semiconductor structures.
Allowable Subject Matter
Claims 12, 15-19 & 21 are allowed.
Response to Arguments
With respect to claim 1, the Examiner maintains that the prior art continues to read on the claim features as addressed in the rejection above. Further, as mentioned during the interview, the ambiguity surrounding the limitation “substrate” remains in the claim that needs correction/clarification.
The amended independent claims 12 and 21 overcomes the prior art rejection and are allowable.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TIMOR KARIMY whose telephone number is (571)272-9006. The examiner can normally be reached Monday - Friday: 8:30 AM -5:00 PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eva Montalvo can be reached at (571) 270-3829. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/TIMOR KARIMY/Primary Examiner, Art Unit 2818
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