DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election of claims 1-9 & 11-20 in the reply filed on 12/09/2025 is acknowledged.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-2 & 18 are rejected under 35 U.S.C. 102(a)(1) and/or 102(a)(2) as being anticipated by SON et al. (US Pub. 2019/0326316).
Regarding claim 1, as best understood, SON teaches a nonvolatile memory device comprising:
a peripheral circuit structure (100, 110 & 160) comprising a peripheral circuit (152 or 154) and a first insulating structure 160 covering the peripheral circuit (Fig. 3A & 31); and
a cell array structure bonded to the peripheral circuit structure and comprising a cell region I and a connection region II (see Fig. 3A below), the cell array structure including
a common source line layer 240;
a buffer insulating layer (230, 315) on the common source line layer 240 (Fig. 3A & Fig.31);
a plurality of contact stop layers (lower wiring 224) separated from the common source line layer 240 and buried in the buffer insulating layer (Fig. 3A & 31);
a cell stack 315/470 including a plurality of gate electrodes 485a and a plurality of insulating layers 315 alternately stacked on the buffer insulating layer (230, 315), and in which the plurality of gate electrodes have a staircase shape in the connection region (see Fig. 3A & Fig. 31);
a plurality of cell channel structures (structure on the left of Fig. 4A & 31, e.g., note 400 & 360) extending to the common source line layer 240 by passing through the cell stack and the buffer insulating layer in the cell region I (Fig. 3A & Fig. 31);
a plurality of contact structures 510 respectively in contact with the plurality of contact stop layers 224 by passing through the cell stack 315/470 in the connection region, and each connected to one or more of the plurality of gate electrodes 485 (Fig. 3A & Fig. 30-31); and
a second insulating structure 230 in contact with the first insulating structure 160 covering the cell stack (see Fig. 3A & Fig. 31).
PNG
media_image1.png
868
1154
media_image1.png
Greyscale
Regarding claim 2, as best understood, SON teaches the nonvolatile memory device of claim 1, wherein the plurality of contact structures 510 and the plurality of contact stop layers 224 in contact with each other are formed together and integrated (Fig. 3A & Fig. 31).
Regarding claim 18, as best understood, SON teaches a memory system comprising:
a nonvolatile memory device comprising a peripheral circuit structure comprising a peripheral circuit (152 or 154) and a first insulating structure 160 covering the peripheral circuit, and a cell array structure bonded to the peripheral circuit structure (see Fig. 3A above) and comprising a cell region I and a connection region II (see annotations on Fig. 3A above); and
a memory controller electrically connected to the nonvolatile memory device and configured to control the nonvolatile memory device (it is understood that the memory device has memory controller),
the cell array structure comprising a common source line layer 240 (Fig. 3A);
a buffer insulating layer (230, 315) on the common source line layer 240 (Fig. 3A & Fig.31);
a plurality of contact stop layers (lower wiring 224) separated from the common source line layer 240 and buried in the buffer insulating layer (Fig. 3A & 31);
a cell stack 315/470 including a plurality of gate electrodes 485a and a plurality of insulating layers 315 alternately stacked on the buffer insulating layer (230, 315), and in which the plurality of gate electrodes have a staircase shape in the connection region (see Fig. 3A & Fig. 31);
a plurality of cell channel structures (structure on the left of Fig. 4A & 31, e.g., 400 & 360) extending to the common source line layer 240 by passing through the cell stack and the buffer insulating layer in the cell region I (Fig. 3A & Fig. 31);
a plurality of contact structures 510 respectively in contact with the plurality of contact stop layers 224 by passing through the cell stack 315/470 in the connection region, and each connected to one or more of the plurality of gate electrodes 485 (Fig. 3A & Fig. 30-31); and
a second insulating structure 230 in contact with the first insulating structure 160 covering the cell stack (see Fig. 3A & Fig. 31).
Allowable Subject Matter
Claims 11-17 are allowed.
The following is an examiner’s statement of reasons for allowance:
With respect to claim 11, the prior art of record fails to teach or suggest in combination with other claim features, a nonvolatile memory device comprising: a second interconnect structure electrically connected to the plurality of cell channel structures and the plurality of contact structures, a plurality of second bonding pads electrically connected to the second interconnect structure, and a second insulating structure surrounding the cell stack, the second interconnect structure, and the plurality of second bonding pads on the common source line layer, the second insulating structure being in contact with the first insulating structure, the plurality of second bonding pads bonded to the peripheral circuit structure to correspond to the plurality of first bonding pads, and the cell region and the connection region are included.
Claims 12-17 are allowed as being directly or indirectly dependent of the allowed independent base claim 11.
Claims 3-9 and 19-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TIMOR KARIMY whose telephone number is (571)272-9006. The examiner can normally be reached Monday - Friday: 8:30 AM -5:00 PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eva Montalvo can be reached at (571) 270-3829. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/TIMOR KARIMY/Primary Examiner, Art Unit 2818
Prosecution Insights