DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election with traverse of Species IV, FIG. 6C in the reply filed on January 8, 2026 is acknowledged. The traversal is on the ground(s) that the species are not mutually exclusive, and that there would not be a serious burden if the Examiner is forced to examine all of the species. This is not found persuasive because there would be a serious search and examination burden since a search for one embodiment would not necessarily result in art applicable to all embodiments.
The requirement is still deemed proper and is therefore made FINAL.
Applicant states claims 1-8, 12-13, 15-17, 19-20 reads on the elected Species IV: FIG. 6C.
Regarding claim 6. Claim 6 recites the limitation “wherein the first cell is configured to receive a booth encoded first operand via the first input pin group; receive a second operand via the second input pin group and the third input pin group; and output a partial product” in the claim language
Applicant’s specification states in the PGPub (Lee et al U.S. 2024/0128257) of the instant application in [0055] In some example embodiments, the cell C80 may be included in a multiplier. For example, the input bit signals A0 to A4 may correspond to at least a portion of a first operand, the input bit signals X1 and/or X2 may correspond to at least a portion of a booth encoded second operand, and the output bit signals Y0 to Y3 may correspond to a partial product. When the first to fourth logic circuits LC1 to LC4 are provided as four independent OAI22 cells, 20 routings may be required, or sufficient, for input pins and output pins. The cell C80 of FIG. 8 may require 11 routings for the first to seventh input pins PI1 to PI7 and the first to fourth output pins PO1 to PO4, and accordingly, available routing resources may increase.
Claim 6 is directed non-elected Species VI: FIG. 8.
Regarding claim 16. Claim 16 recites the limitation “a second logic circuit configured to generate an output bit signal based on the internal bit signal received from the first logic circuit and on second input bit signals received via the second input pin group” in the 8-10 lines in the claim language.
Applicant’s specification states in the PGPub of the instant application in [0059] Referring to FIG. 10A, the cell C101 may include the first logic circuit LC1 and/or the second logic circuit LC2. The first logic circuit LC1 may correspond to an AOI22 logic, and the second logic circuit LC2 may correspond to a 4-input NAND gate. The first logic circuit LC1 may generate an internal bit signal INT from the input bit signals A0, A1, B0, and/or B1. The second logic circuit LC2 may generate the output bit signal Y from input bit signals A, B, and/or D and/or the internal bit signal INT.
Claim 16 is directed non-elected Species VII: FIG. 10A.
Claims 17-20 depends upon independent claim 16.
Claims 6, 9-11, 14, 16-20 withdrawn from further consideration pursuant to 37 CFR 1.142(b), as being drawn to a nonelected species, there being no allowable generic or linking claim. Applicant timely traversed the restriction (election) requirement in the reply filed on January 8, 2026.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on October 5, 2023 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-5, 7-8, 12, 13, and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Sio et al (U.S. 2022/0238442) and Viau et al (U. S. 2013/0002303).
Regarding claim 1. Sio et al disclose an integrated circuit (FIG. 2, item 200) comprising a plurality of cells (FIG. 2, item 270,280,290) in a series of rows ([0033]), wherein
a first cell (FIG. 2, item 280) of the plurality of cells (FIG. 2, item 270, 280, 290) includes
a logic circuit ([0046]).
Sio et al fails to explicitly disclose
a first cell includes
a plurality of logic circuits, each logic circuit of the plurality of logic circuits configured to independently generate an output bit signal according to input bit signals,
a first input pin group including at least one input pin commonly connected to the plurality of logic circuits,
a second input pin group including at least one input pin commonly connected to two or more logic circuits among the plurality of logic circuits, and a third input pin group including at least one input pin respectively connected exclusively to at least one of the plurality of logic circuits.
However, Viau et al teaches
a first cell (FIG. 3A-3C, item 300) includes
a plurality of logic circuits (FIG. 3C, items 302,304,306,308; [0030]-[0032]), each logic circuit (FIG. 3C, items 302,304,306,308; [0030]-[0032]) of the plurality of logic circuits (FIG. 3C, items 302,304,306,308) configured to independently generate ([0031]) an output bit signal ([0029], i.e. outputs 406, 408, 410 and 412) according to input bit signals ([0029], i.e. inputs 386, 388, 390, 392, 394, 396, 398, 400, 402 and 404),
a first input pin group (FIG. 3C, item 388) including at least one input pin commonly connected ([0033], i.e. the two logic inputs 388 and 392 are common to four instances of an OAI gate (302, 304, 306 and 308) and short together the internal stack nodes on these four gates) to the plurality of logic circuits (FIG. 3C, items 302, 304, 306, 308),
a second input pin group (FIG. 3C, item 392) including at least one input pin commonly connected ([0033]) to two or more logic circuits ([0030]) among the plurality of logic circuits (FIG. 3C, items 302,304,306,308), and
a third input pin group (FIG. 3C, items 390, 396, 400, 404) including at least one input pin ([0029]) respectively connected exclusively to at least one (FIG. 3C, items 302,304,306,308) of the plurality of logic circuits (FIG. 3C, items 302,304,306,308).
Since Sio et al and Viau et al teach circuit using OR-AND-INVERT circuits, it would have been obvious to one having ordinary skill in the art of semiconductors before the effective filing date of the claimed invention to have combined the integrated circuit as disclosed to modify Sio et al with the teachings of a first cell includes a plurality of logic circuits, each logic circuit of the plurality of logic circuits configured to independently generate an output bit signal according to input bit signals, a first input pin group including at least one input pin commonly connected to the plurality of logic circuits, a second input pin group including at least one input pin commonly connected to two or more logic circuits among the plurality of logic circuits, and a third input pin group including at least one input pin respectively connected exclusively to at least one of the plurality of logic circuits as disclosed by Viau et al. The use of four instances of an OAI gate and short together the internal stack nodes on these four gates in Viau et al provides for reducing sizes of the transistors to save silicon area. Second, a greater total drive strength may be achieved by using smaller devices (Viau et al, [0033]).
Regarding claim 2. Sio et al and Viau et al discloses the integrated circuit of claim 1 above.
Viau et la further discloses wherein the plurality of logic circuits (FIG. 3C, items 302,304,306,308) correspond to an identical logic ([0029]) .
Regarding claim 3. Sio et al and Viau et al discloses the integrated circuit of claim 2 above.
Viau et la further discloses wherein each logic circuit ([0029]-[0034]) of the plurality of logic circuits (FIG. 3C, items 302,304,306,308) corresponds to an OAI22 logic ([0029]-[0034]) including a first OR gate ([0029]-[0034]) having a first input ([0029]-[0034]) and a second input ([0029]-[0034]), a second OR gate ([0029]-[0034]) having a third input ([0029]-[0034]) and a fourth input ([0029]-[0034]), and a NAND gate ([0029]-[0034]).
Regarding claim 4. Sio et al and Viau et al discloses the integrated circuit of claim 3 above.
Viau et la further discloses
wherein the plurality of logic circuits (FIG. 3C, items 302,304,306,308) includes first to fourth logic circuits (FIG. 3C, items 302,304,306,308) respectively connected to first to fourth output pins ([0029], i.e. outputs 406, 408, 410 and 412), and
the first input pin group (FIG. 3C, item 388) includes a first input pin (FIG. 3C, item 388) connected to a first input of each (FIG. 3C, item 388) of the first to fourth logic circuits (FIG. 3C, items 302,304,306,308), and
a second input pin ([0029], i.e. inputs 386, 392, 394, 398, 402) connected to a third input ([0029], i.e. inputs 386, 392, 394, 398, 402) of each of the first to fourth logic circuits (FIG. 3C, items 302,304,306,308).
Regarding claim 5. Sio et al and Viau et al discloses the integrated circuit of claim 4 above.
Viau et la further discloses
wherein the third input pin group (FIG. 3C, items 390, 396, 400, 404) includes
a third input pin (FIG. 3C, items 390) connected to a second input (FIG. 3C, items 390) of the first logic circuit (FIG. 3C, items 302), and
a seventh input pin (FIG. 3C, item 404) connected to a fourth input (FIG. 3C, item 404) of the fourth logic circuit (FIG. 3C, items 308), and
the second input pin group (FIG. 3C, item 392) includes
a fourth input pin (FIG. 3C, item 392) connected to a fourth input (FIG. 3C, item 392) of the first logic circuit (FIG. 3C, items 302) and a second input (FIG. 3C, item 392) of the second logic circuit (FIG. 3C, items 304),
a fifth input pin (FIG. 3C, item 392) connected to a fourth input (FIG. 3C, item 392) of the second logic circuit (FIG. 3C, items 304) and a second input (FIG. 3C, item 392) of the third logic circuit (FIG. 3C, items 306), and
a sixth input pin (FIG. 3C, item 392) connected to a fourth input (FIG. 3C, item 392) of the third logic circuit (FIG. 3C, items 306) and a second input (FIG. 3C, item 392) of the fourth logic circuit (FIG. 3C, items 308).
Regarding claim 7. Sio et al and Viau et al discloses the integrated circuit of claim 3 above.
Sio et al further discloses
wherein the first cell (FIG. 2, item 280) is in one row (FIG. 2, item 203) or two or more rows adjacent to each other, among the series of rows ([0033]).
Regarding claim 8. Sio et al disclose an integrated circuit (FIG. 2, item 200) comprising a plurality of cells (FIG. 2, item 270,280,290) in a series of rows ([0033]), wherein
a first cell (FIG. 2, item 280) of the plurality of cells (FIG. 2, item 270,280,290) includes
a logic circuit ([0046]).
Sio et al fails to explicitly disclose
a first cell includes
a plurality of logic circuits, each logic circuit of the plurality of logic circuits corresponding to an identical logic and configured to independently generate an output bit signal according to input bit signals,
a first input pin group including at least one input pin commonly connected to the plurality of logic circuits, and
a second input pin group including a plurality of input pins respectively connected exclusively to the plurality of logic circuits.
However, Viau et al teaches
a first cell (FIG. 3A-3C, item 300) includes
a plurality of logic circuits (FIG. 3C, items 302,304,306,308; [0030]-[0032]), each logic circuit (FIG. 3C, items 302,304,306,308; [0030]-[0032]) of the plurality of logic circuits (FIG. 3C, items 302,304,306,308) corresponding to an identical logic ([0029]) and configured to independently generate ([0031]) an output bit signal ([0029], i.e. outputs 406, 408, 410 and 412) according to input bit signals ([0029], i.e. inputs 386, 388, 390, 392, 394, 396, 398, 400, 402 and 404),
a first input pin group (FIG. 3C, item 388, 392) including at least one input pin (FIG. 3C, item 388) commonly connected ([0033], i.e. the two logic inputs 388 and 392 are common to four instances of an OAI gate (302, 304, 306 and 308) and short together the internal stack nodes on these four gates) to the plurality of logic circuits (FIG. 3C, items 302,304,306,308), and
a second input pin group ([0029], i.e. inputs 386, 390, 394, 396, 398, 400, 402 and 404) including a plurality of input pins ([0029], i.e. inputs 386, 390, 394, 396, 398, 400, 402 and 404) respectively connected exclusively (FIG. 3A-3C; [0029]-[0032]) to the plurality of logic circuits (FIG. 3C, items 302,304,306,308).
Since Sio et al and Viau et al teach circuit using OR-AND-INVERT circuits, it would have been obvious to one having ordinary skill in the art of semiconductors before the effective filing date of the claimed invention to have combined the integrated circuit as disclosed to modify Sio et al with the teachings of a first cell includes a plurality of logic circuits, each logic circuit of the plurality of logic circuits corresponding to an identical logic and configured to independently generate an output bit signal according to input bit signals, a first input pin group including at least one input pin commonly connected to the plurality of logic circuits, and a second input pin group including a plurality of input pins respectively connected exclusively to the plurality of logic circuits as disclosed by Viau et al. The use of four instances of an OAI gate and short together the internal stack nodes on these four gates in Viau et al provides for sizes of the transistors may be reduced to save silicon area. Second, a greater total drive strength may be achieved by using smaller devices (Viau et al, [0033]).
Regarding claim 12. Sio et al and Viau et al discloses the integrated circuit of claim 8 above.
Viau et la further discloses
wherein the first input pin group (FIG. 3C, item 388, 392) includes a first input pin (FIG. 3C, item 388) and a second input pin (FIG. 3C, item 392), and
each of the plurality of logic circuits (FIG. 3C, items 302,304,306,308; [0030]-[0032]) corresponds to a logic including
a first logic gate ([0031], i.e. present invention may also be applicable to a CMOS circuit including AND-OR-INVERT (AOI) gates) connected to the first input pin (FIG. 3C, item 388) and one of a plurality of input pins (FIG. 3C, item 390) included in the second input pin group ([0029], i.e. inputs 386, 390, 394, 396, 398, 400, 402 and 404),
a second logic gate ([0031], i.e. present invention may also be applicable to a CMOS circuit including AND-OR-INVERT (AOI) gates) connected to the second input pin (FIG. 3C, item 392) and another one of the plurality of input pins (FIG. 3C, item 386) included in the second input pin group ([0029], i.e. inputs 386, 390, 394, 396, 398, 400, 402 and 404), and
a third logic gate ([0031], i.e. present invention may also be applicable to a CMOS circuit including AND-OR-INVERT (AOI) gates) configured to receive an output bit signal ([0029]-[0034]) of the first logic gate and an output bit signal ([0029]-[0034]) of the second logic gate ([0029]-[0034]).
Regarding claim 13. Sio et al and Viau et al discloses the integrated circuit of claim 12 above.
Viau et la further discloses
wherein each of the plurality of logic circuits (FIG. 3C, items 302,304,306,308) corresponds to an OAI22 logic ([0029]-[0034]) in which each of the first logic gate ([0029]-[0034]) and the second logic gate ([0029]-[0034]) is an OR gate ([0029]-[0034]) and the third logic gate ([0029]-[0034]) is a NAND gate ([0029]-[0034]).
Regarding claim 15. Sio et al and Viau et al discloses the integrated circuit of claim 8 above.
Sio et al further discloses
wherein the first cell (FIG. 2, item 280) is in one row (FIG. 2, item 203) or two or more rows adjacent to each other, among the series of rows ([0033]).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SCOTT E BAUMAN whose telephone number is (469)295-9045. The examiner can normally be reached M-F, 9-5 CST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Joshua Benitez can be reached at 571-270-1435. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/S.E.B./ Examiner, Art Unit 2815 /JOSHUA BENITEZ ROSARIO/Supervisory Patent Examiner, Art Unit 2815
Prosecution Insights