DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
a. As to claim 1 it is unclear if the recitation of “wherein the plurality of insulating frames overlap a plurality of corner regions of the one of the plurality of semiconductor chips in a direction in which the plurality of semiconductor chips face each other” is meant to mean that each of the plurality overlaps a plurality of corners or that the frames overlap corresponding corners.
b. As to claims 2-3, 11, 16 and 19-20, It is unclear what constitutes a “boundary lines” further applicant has not established that frames have more than one boundary line.
c. As to claim 8, claim 8 appear to contradict claim 1. Claim 1 requires the frames to be on the chip claim 8 requires them to be spaced apart : wherein the plurality of insulating frames is spaced apart from the one of the pluralities of semiconductor chips. Thus, it is unclear how the frames can be on the one chip but spaces apart from the one chip. It appears the claim should be wherein the plurality of insulating frames are spaced apart from another of the plurality of semiconductor chips.
d. As to claim 11 photosensitive polyimide should be a photosensitive polyimide.
e. As to claim 14, 15, and 20 it is unclear what is meant by “wherein an arrangement of the plurality of bumps protrudes toward a space between the plurality of insulating frames”. The individual bumps individually do not appear to protrude. Applicant points to figures 5 and 6 for this recitation. The best the examiner can understand is that the bump arrangements are between the frames.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1 2-3, 15-16 and 19-20 is is/are rejected under 35 U.S.C. 102a1 as being anticipated by Choe 10,020,290 using claim 10 as evidence.
Choe teaches a semiconductor package, comprising: a plurality of semiconductor chips that face each other (items 200,210,220 230 and 300); a plurality of bumps disposed on a front surface or a rear surface of one of the plurality of semiconductor chips (208 218 228 and 238); an underfill layer that surrounds the plurality of bumps (portions of 201 209 219 229 and 239); and a plurality of insulating frames spaced apart from each other on the front or rear surface of the one of the plurality of semiconductor chips ((portions of 201 209 219 229 and 239 at the corners) , wherein the plurality of insulating frames overlap a plurality of corner regions of the one of the plurality of semiconductor chips in a direction in which the plurality of semiconductor chips face each other ( the corner areas of the underfill).
Claim 10 requires wherein the plurality of insulating frames and the underfill layer contain different insulating materials.
Thus claim 1 envisions that the frames and the underfill can be the same material. Since claim 1 must be broader than claim 1. Thus, the definition of frames is arbitrary since the frames can be portions of the underfill.
b. As to claims 2-3, 15, 16 and 19-20 Choe teaches that bumps are between the arbitrarily defined frames since they are parts of the underfill. Further the shapes are arbitrary thus they can be defined to have wherein, in each of the plurality of insulating frames, one boundary line has an oblique direction with respect to remaining boundary lines and wherein the remaining boundary lines of each of the plurality of insulating frames are parallel to boundary lines of the plurality of corner regions of the one of the plurality of semiconductor chips.
Claim(s) 1,4,6,8,10, 14, and 15 is/are rejected under 35 U.S.C. 102a1 as being anticipated by Chen 11069661.
a. As to claims 1,14 and 15, Chen teaches A semiconductor package, comprising: a plurality of semiconductor chips that face each other (figure 1 items 11 and 12); a plurality of bumps disposed on a front surface or a rear surface of one of the plurality of semiconductor chips(item 13); an underfill layer that surrounds the plurality of bumps (item 14: The first encapsulating portion 14 is a underfill material in a fluid state with the coefficients of thermal expansion (CTE) approximately between 52 and 109); and a plurality of insulating frames spaced apart from each other on the front or rear surface of the one of the plurality of semiconductor chips (item 15 it must be insulating otherwise the 13 would be shorted see figure 1’ for the plurality item 15),wherein the plurality of insulating frames overlap a plurality of corner regions of the one of the plurality of semiconductor chips in a direction in which the plurality of semiconductor chips face each other (figure 1’ item 15 overlaps the corners).
Chen teaches wherein an arrangement of the plurality of bumps protrudes toward a space between the plurality of insulating frames (the bumps are between the frames figure 1).
b. As to claim 4, Chen teaches wherein the underfill layer contacts each of the plurality of insulating frames (item 14 contact item 15 figure 1 and 1’).
c. As to claim 6 Chen teaches wherein a maximum separation distance between adjacent insulating frames of the plurality of insulating frames ( the maximum separation distance is a distance from far edge/outer edge of a frame to an outer edge of another frame item 15) is longer than a maximum length, in the same direction as a direction of the maximum separation distance, of each of adjacent insulating frames of the plurality of insulating frames (the maximum separation distance is long since it include the length).
c. As to claim 8, Chen teaches wherein the plurality of insulating frames are spaced apart from another of the plurality of semiconductor chips figure 1.
f. As to claim 10, Chen teaches wherein the plurality of insulating frames and the underfill layer contain different insulating materials (they are different CTE materials).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 5, 11-12, 13 and 15-17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Choe 10,020,290 cited on Ids in view of Chen.
a. As to claim 1 and 5, Choe teaches a semiconductor package, comprising: a plurality of semiconductor chips that face each other (items 200-230 and 300 figure 1) ; a plurality of bumps disposed on a front surface or a rear surface of one of the plurality of semiconductor chips (item 206, 216,226, 237); an underfill layer that surrounds the plurality of bumps (209,219,229, 239); Choe teaches a protruding portion of the underfill layer does not overlap the one of the plurality of semiconductor chips in a direction in which the plurality of semiconductor chips face each other (see 209,219,229, 239 figure 1).
Choe does not teaches a plurality of insulating frames spaced apart from each other on the front or rear surface of the one of the plurality of semiconductor chips, wherein the plurality of insulating frames overlap a plurality of corner regions of the one of the plurality of semiconductor chips in a direction in which the plurality of semiconductor chips face each other wherein the underfill layer protrudes beyond spaces between adjacent insulating frames of the plurality of insulating frames (assuming the frames are a different material than the underfill).
Chen teaches providing a second encapsulating material at the corners (item 15 figures 1 and 1’ of the chips) to prevent cracking:
However, in a conventional MCM, such as that described in prior art 1, a gap exists between an upper die and a lower die, which makes the dies susceptible to warpage or even cracks during subsequent high temperature processes.
Moreover, in prior art 1, conductive bumps (e.g., reference numeral 39) for electrically connecting the upper and lower dies are not encapsulated by an encapsulant (e.g., reference numeral 38), therefore the stress of these conductive bumps cannot be effectively distributed, resulting in warpage of the dies. This creates a shift in the alignment between the upper and lower dies and significantly affects the electrical connections between the upper and lower dies, lowering the yield and the reliability of the products. Moreover, as the number of layers of dies stacked to each other increases, stress accumulates and warpage towards the same direction becomes more prominent, which makes the dies more prone to cracks.
Chen shows the second encapsulating to be flush with edges of the chip (fig 1 and 1’).
Chen teaches providing a second encapsulating material at the corners (item 15 figures 1 and 1’ of the chips) flush with the sidewalls.
Thus, it would have been obvious to one of ordinary skill in the art at the time of filing to provide the second encapsulation adjacent at the corners the underfill of a different CTE material to prevent cracking in the chips.
Thus, the underfill would protrude from the frames item 15 as suggest by Choe in view of Chen.
b. As to claims 1, 11 and 12 applicants has not defined with any sufficiency which direction is a top/bottom or above/below front/rear.
Choe teaches A semiconductor package, comprising: a plurality of semiconductor chips that face each other (items 200-230 and 300 figure 1) ; a plurality of bumps disposed on a front surface or a rear surface of one of the plurality of semiconductor chips (item 206, 216,226, 237); an underfill layer that surrounds the plurality of bumps (209,219,229, 239); Choe teaches a protruding portion of the underfill layer does not overlap the one of the plurality of semiconductor chips in a direction in which the plurality of semiconductor chips face each other (see 209,219,229, 239 figure 1).
Choe further a semiconductor substrate(items 203,211,221,221,231 see also 204 they through silicon vias silicon is a semiconductor ) that includes through-electrodes (items 204, 214,224, 234); a device layer disposed below the semiconductor substrate (a portion of 202,212,222 232) ; a rear/front surface passivation layer disposed on the semiconductor substrate and that provides a rear/front surface (the remaining portion of 202,212 222 232); and rear/front pads connected to the through-electrodes and disposed on the rear/front surface passivation layer (figure 1) and the frames are in contact with the front/rear surface (items 202,212 222 232 are in contact with the underfill/encapsulation)
Choe does not teaches a plurality of insulating frames spaced apart from each other on the front or rear surface of the one of the plurality of semiconductor chips, wherein the plurality of insulating frames overlap a plurality of corner regions of the one of the plurality of semiconductor chips in a direction in which the plurality of semiconductor chips face each other wherein the underfill layer protrudes beyond spaces between adjacent insulating frames of the plurality of insulating frames (assuming the frames are a different material than the underfill).
Chen teaches providing a second encapsulating material at the corners (item 15 figures 1 and 1’ of the chips) to prevent cracking:
However, in a conventional MCM, such as that described in prior art 1, a gap exists between an upper die and a lower die, which makes the dies susceptible to warpage or even cracks during subsequent high temperature processes.
Moreover, in prior art 1, conductive bumps (e.g., reference numeral 39) for electrically connecting the upper and lower dies are not encapsulated by an encapsulant (e.g., reference numeral 38), therefore the stress of these conductive bumps cannot be effectively distributed, resulting in warpage of the dies. This creates a shift in the alignment between the upper and lower dies and significantly affects the electrical connections between the upper and lower dies, lowering the yield and the reliability of the products. Moreover, as the number of layers of dies stacked to each other increases, stress accumulates and warpage towards the same direction becomes more prominent, which makes the dies more prone to cracks.
Thus, it would have been obvious to one of ordinary skill in the art at the time of filing to provide the second encapsulation adjacent at the corners the underfill of a different CTE material to prevent cracking in the chips.
Choe and Chen do no teach the material of the frame in PID or PSPI however both were known at the time of filing for underfill encapsulation.
Further, it would have been obvious to one of ordinary skill in the art at the time of filing to use either PID material or PSPI for the second encapsulation to optimize the flow and the CTE of the material for the desired results.
b. As to claim 13, Cho teaches 300 maybe larger:
Next, the upper semiconductor chip 300 is disposed on the plurality of semiconductor chips 200, 210, 220, and 230. For example, the upper semiconductor chip 300 may be additionally stacked in the stack structure including the plurality of semiconductor chips 200, 210, 230, and 230. For example, FIG. 1 illustrates that the upper semiconductor chip 300 is connected with the semiconductor chip 230 through the contact pad 238. In the various embodiments, a thickness, i.e., along the y-axis, of the upper semiconductor chip 300 may be larger than those of the semiconductor chips 200, 210, 220, and 230. In several embodiments, the upper semiconductor chip 300 may include a memory chip, a logic chip, and the like similar to the plurality of semiconductor chips 200, 210, 220, and 230.
c. As to claims 1, 15, 17-18, applicant has not defined with any sufficiency which direction is a top/bottom or above/below front/rear.
Choe teaches A semiconductor package, comprising: a plurality of semiconductor chips that face each other (items 200-230 and 300 figure 1) ; a plurality of bumps disposed on a front surface or a rear surface of one of the plurality of semiconductor chips (item 206, 216,226, 237); an underfill layer that surrounds the plurality of bumps (209,219,229, 239); Choe teaches a protruding portion of the underfill layer does not overlap the one of the plurality of semiconductor chips in a direction in which the plurality of semiconductor chips face each other (see 209,219,229, 239 figure 1).
Chloe further a semiconductor substrate(items 203,211,221,221,231 see also 204 they through silicon vias silicon is a semiconductor ) that includes through-electrodes (items 204, 214,224, 234); a device layer disposed below the semiconductor substrate (a portion of 202,212,222 232) ; a rear/front surface passivation layer disposed on the semiconductor substrate and that provides a rear/front surface (the remaining portion of 202,212 222 232); and rear/front pads connected to the through-electrodes and disposed on the rear/front surface passivation layer (figure 1) and the frames are in contact with the front/rear surface (items 202,212 222 232 are in contact with the underfill/encapsulation)
Choe does not teaches a plurality of insulating frames spaced apart from each other on the front or rear surface of the one of the plurality of semiconductor chips, wherein the plurality of insulating frames overlap a plurality of corner regions of the one of the plurality of semiconductor chips in a direction in which the plurality of semiconductor chips face each other wherein the underfill layer protrudes beyond spaces between adjacent insulating frames of the plurality of insulating frames (assuming the frames are a different material than the underfill).
Chen teaches providing a second encapsulating material at the corners (item 15 figures 1 and 1’ of the chips) to prevent cracking:
However, in a conventional MCM, such as that described in prior art 1, a gap exists between an upper die and a lower die, which makes the dies susceptible to warpage or even cracks during subsequent high temperature processes.
Moreover, in prior art 1, conductive bumps (e.g., reference numeral 39) for electrically connecting the upper and lower dies are not encapsulated by an encapsulant (e.g., reference numeral 38), therefore the stress of these conductive bumps cannot be effectively distributed, resulting in warpage of the dies. This creates a shift in the alignment between the upper and lower dies and significantly affects the electrical connections between the upper and lower dies, lowering the yield and the reliability of the products. Moreover, as the number of layers of dies stacked to each other increases, stress accumulates and warpage towards the same direction becomes more prominent, which makes the dies more prone to cracks.
Chen teaches wherein an arrangement of the plurality of bumps protrudes toward a space between the plurality of insulating frames (the bumps are between the frames figure 1).
Thus, it would have been obvious to one of ordinary skill in the art at the time of filing to provide the second encapsulation adjacent the underfill of a different CTE material , with the bumps extending between the regions of second encapsulation to prevent cracking in the chips.
Claim Rejections - 35 USC § 103
Claim(s) 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen
a. As to claim 7, Chen does not explicitly teach wherein a thickness of each of the plurality of insulating frames is greater than 1 μm and less than 10 μm.
However, inter die spacing for stacks of dies was know to be greater than 1 micron a less than 10 microns.
Thus, it would have been obvious to form the encapsulations to be greater than 1 micron but less than 10 microns to optimize the stacking size to all more chips to be bonded in the same laminate space.
Claim Rejections - 35 USC § 103
Claim(s) 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen in view of Lu 20130234320.
Chen does not wherein a portion of the underfill layer overlaps the plurality of insulating frames in a direction in which the plurality of semiconductor chips face each other.
Lu teaches that in interfacial regions between encapsulations 130b and 140 that there exist overlap regions.
Thus, it would have been obvious to one of ordinary skill in the art at the time of filing to form an overlap in the interfacial region as suggest by Lu to use conventional structure to derive expected results of the dual encapsulations.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MATTHEW L REAMES whose telephone number is (571)272-2408. The examiner can normally be reached M-Th 6:00 am-4:00 pm EST.
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/MATTHEW L. REAMES/
Primary Examiner
Art Unit 2896
/MATTHEW L REAMES/Primary Examiner, Art Unit 2896