Office Action Predictor
Last updated: April 15, 2026
Application No. 18/481,855

APPARATUSES AND METHODS INCLUDING CIRCUITS IN GAP REGIONS OF A MEMORY ARRAY

Non-Final OA §103
Filed
Oct 05, 2023
Examiner
HOANG, HUAN
Art Unit
2827
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Micron Technology, INC.
OA Round
2 (Non-Final)
93%
Grant Probability
Favorable
2-3
OA Rounds
1y 8m
To Grant
96%
With Interview

Examiner Intelligence

Grants 93% — above average
93%
Career Allow Rate
1123 granted / 1206 resolved
+25.1% vs TC avg
Minimal +3% lift
Without
With
+3.0%
Interview Lift
resolved cases with interview
Fast prosecutor
1y 8m
Avg Prosecution
21 currently pending
Career history
1227
Total Applications
across all art units

Statute-Specific Performance

§101
1.4%
-38.6% vs TC avg
§103
24.6%
-15.4% vs TC avg
§102
34.6%
-5.4% vs TC avg
§112
19.2%
-20.8% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1206 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . The Amendment filed on 10/02/2025 has been received and entered. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Cho (US 2006/0023536 cited in the last office action) in view of Kwack (US 2011/0026337). Regarding claim 8, Cho (Fig. 3) shows an apparatus, comprising: first and second memory mats (BANKO and BANK1) adjacent along a first direction, the first and second memory mats including memory cells; a region (MA01) between the first and second memory mats along the first direction, the region including a local input/output (LIO) line that extends along a second direction perpendicular to the first direction through the region (the lio and the lioB extend from nodes A and B along a second direction to the global input/output line gio), and further including a LIO driver and a LIO precharge circuit (110) coupled to the LIO line, and the LIO precharge circuit configured to provide a LIO precharge voltage to the LIO lines Cho does not the LIO driver configured to drive the LIO line to data voltage levels based on data read from the memory cells or based on data to be written to the memory cells. However, Kwack discloses the first input/output driver 21 writes or reads data into/from memory cells of the first memory bank 11 through local input/output lines (e.g., LIO_up0) (Figs. 1-3). It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify Cho by using an input/output driver to drive the local input/output line to data voltage levels data read from the memory cells or based on data to be written to the memory cells. Response to Arguments Applicant’s arguments with respect to claim 8 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. Allowable Subject Matter Claims 1-7 and 17-21 are allowed. Claims 9-16 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Regarding claim 1, the prior art made of record and considered pertinent to the applicant's disclosure does not teach the claimed limitation of “an activation voltage driver circuit included in a second gap region, the second gap region including a boundary shared with the first gap region, and including a first corner at a corner of the first memory mat and further including a second corner at a corner of the second memory mat, the activation voltage driver circuit configured to provide an activation voltage to the sense amplifiers.” in combination with the other limitations thereof as is recited in the claim. Claims 2-7 depend on claim 1. Regarding claim 9, the prior art made of record and considered pertinent to the applicant's disclosure does not teach the claimed limitation of “a second region adjacent the region in the second direction, the second region including a first activation voltage driver circuit configured to provide a first activation voltage to sense amplifiers included in the region between the first and second memory mats along the first direction.” in combination with the other limitations thereof as is recited in the claim. Claims 10 and 11 depend on claim 9. Regarding claim 12, the prior art made of record and considered pertinent to the applicant's disclosure does not teach the claimed limitation of “a conductive activation voltage mesh including conductive lines that extend in the second direction in the region, the conductive activation voltage mesh configured to provide an activation voltage to circuits included in the region.” in combination with the other limitations thereof as is recited in the claim. Claims 13-16 depend on claim 12. Regarding claim 17, the prior art made of record and considered pertinent to the applicant's disclosure does not teach the claimed limitation of “a conductive activation voltage mesh coupled to the activation voltage driver circuit and the sense amplifiers to provide the activation voltage from the activation voltage driver circuit in the second region to the sense amplifiers in the first region, the conductive activation voltage mesh including conductive lines extending along a second direction perpendicular to the first direction in the first region.” in combination with the other limitations thereof as is recited in the claim. Claims 18-21 depend on claim 17. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to HUAN HOANG whose telephone number is (571)272-1779. The examiner can normally be reached 7:30AM-4:00PM M-F. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, AMIR ZARABIAN can be reached at 571-272-1852. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /HUAN HOANG/ Primary Examiner, Art Unit 2827
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Prosecution Timeline

Oct 05, 2023
Application Filed
Aug 23, 2025
Non-Final Rejection — §103
Oct 02, 2025
Response Filed
Jan 05, 2026
Non-Final Rejection — §103
Apr 06, 2026
Response Filed

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12597462
NON-VOLATILE MEMORY WITH HYBRID ROUTING FOR SHARED WORD LINE SWITCHES
2y 5m to grant Granted Apr 07, 2026
Patent 12592277
DISTRIBUTED WRITE DRIVER FOR MEMORY ARRAY
2y 5m to grant Granted Mar 31, 2026
Patent 12592278
MEMORY DEVICE USING SEMICONDUCTOR ELEMENT
2y 5m to grant Granted Mar 31, 2026
Patent 12586630
MEMORY ARRAY CIRCUIT
2y 5m to grant Granted Mar 24, 2026
Patent 12586618
MEMORY SYSTEM AND MEMORY DIE
2y 5m to grant Granted Mar 24, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

2-3
Expected OA Rounds
93%
Grant Probability
96%
With Interview (+3.0%)
1y 8m
Median Time to Grant
Moderate
PTA Risk
Based on 1206 resolved cases by this examiner. Grant probability derived from career allow rate.

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