DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of Claims
Claims 1-8, 10, 15-19, 24-29, and 32-34 are under consideration in this Office Action.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim 1-5 and 7 are rejected under 35 U.S.C. 102/103 as being unpatentable over Darwish et al., US 2014/0042535 (corresponding to US 9,024379).
In re Claim 1, Darwish discloses a semiconductor device (Fig. (Fig. 4F), comprising: a semiconductor layer structure SLS (Fig. A) that comprises a drift region (marked as 109 marked in Fig, 1 and as DRIFT in Fig. A) having a first n conductivity type, a well layer (marked a 111 in Fig. 1 and marked as W in Fig. A) having a second p conductivity type, and a support shield (marked as 435A in Fig. 4B and as SSh in Fig. A) having the second p conductivity type; and a first gate trench (marked as 119 in Fig. 1 and as 1GT in Fig. A) extending into an upper portion of the semiconductor layer structure SLS, wherein a width Wd of a first (bottom) portion of the support shield SSh decreases with increasing distance from the well region W (Figs. 1, 4 and A; [0034 -0055]).
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Fig. A. Darwish’s Fig. 4F annotated to show the details cited
In re Claim 2, Darwish discloses all limitations of Claim 2 including that the first (bottom) portion of the support shield SSh comprises a portion that is deeper in the semiconductor layer structure SLS than the well layer W, except for that the first (bottom) portion of the support shield SSh comprises a portion is less deep in the semiconductor layer structure SLS than a bottom of the first gate trench 1GT. (Fig. A).
The difference between the Applicant’s Claim 2 and Darwish’s reference is in the specified ratio of the depth location of the first (bottom) portions of the support shield SSh.
It is known in the art that depth is a result effective variable – because volume depends on it. Due to high level of knowledge and skills of personal capable to operate very sophisticated and expensive equipment in semiconductor technology, it would have been an obvious matter of design choice of one of ordinary skill in the semiconductor art to use the first (bottom) portion of the support shield SSh comprising a portion that is less deep in the semiconductor layer structure SLS than a bottom of the first gate trench 1GT, since such a modification would have involved a mere change in the size of a component. In Gardner v. TEC Systems, Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984) (MPEP2144.04.IV.A).
In re Claim 3, Darwish discloses all limitations of Claim 2 except for that an entirety of the support shield SSh that is deeper in the semiconductor layer structure SLS than the well layer W has a width that decreases with increasing distance from the well region W.
The difference between the Applicant’s Claim 3 and Darwish’s reference is in the specified shape of the support shield SSh.
Due to high level of knowledge and skills of personal capable to operate very sophisticated and expensive equipment in semiconductor technology, it would have been an obvious matter of design choice of one of ordinary skill in the semiconductor art to use the well layer W has a width that decreases with increasing distance from the well region W, since such a modification would have involved a mere change in the shape of a component. In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966) (MPEP2144.04.IV.B).
In re Claim 4, Darwish discloses the semiconductor device of Claim 1, wherein a bottom of the first gate trench 1GT has a first depth 1D (Fig. A) from the upper portion of the semiconductor layer structure SLS and a bottom of the support shield SSh has a second depth 2D from the upper portion of the semiconductor layer structure SLS, where the second depth 2D is greater than the first depth 1D.
In re Claim 5, Darwish discloses all limitations of Claim 5 including that the semiconductor layer structure SLS further comprises a trench shielding region TSh having the second p conductivity type below the first gate trench 1GT, where a bottom of the trench shielding region TSh has a third depth 3D from the upper portion of the semiconductor layer structure SLS, (Fig. A), except for that the second depth 2D is greater than the third depth 3D .
The only difference between the Applicant’s Claim 5 and Darwish’s reference is in the specified ratio of the depths. It is known in the art that depth is a result effective variable – because volume depends on it. Due to high level of knowledge and skills of personal capable to operate very sophisticated and expensive equipment in semiconductor technology, it would have been an obvious matter of design choice of one of ordinary skill in the semiconductor art to use the second depth 2D that is greater than the third depth 3D, since such a modification would have involved a mere change in the size of a component. In Gardner v. TEC Systems, Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984) (MPEP2144.04.IV.A).
In re Claim 7, Darwish discloses the semiconductor device of Claim 1, wherein the semiconductor device comprise a MOSFET, and the semiconductor layer structure SLS further comprises a source layer (marked as 115 in Fig. 4 and as S in Fig. A) having the first n conductivity type ([0036]) on the well layer W, and wherein a gate oxide layer (marked as 121 in Fig. 1 and as GO in Fog. A) and a gate electrode 423 are in the first gate trench 1GT, with the gate oxide layer GO between the gate electrode 423 and the semiconductor layer structure SLS .
In re Claim 8, Darwish discloses all limitations of Claim 8 including that a maximum width of a portion of the support shield SSh that horizontally overlaps the source region S is larger than a width of a portion of the support shield SSh that horizontally overlaps a bottom of the first gate trench 1GT, except for that the portion of the support shield SSh that horizontally overlaps the source region S is at least 10% larger than a width of a portion of the support shield SSh that horizontally overlaps a bottom of the first gate trench 1GT.
The only difference between the Applicant’s Claim 8 and Darwish’s reference is in the specified ratio of the widths. It is known in the art that width is a result effective variable – because volume depends on it. Due to high level of knowledge and skills of personal capable to operate very sophisticated and expensive equipment in semiconductor technology, it would have been an obvious matter of design choice of one of ordinary skill in the semiconductor art to use the portion of the support shield SSh that horizontally overlaps the source region S is at least 10% larger than a width of a portion of the support shield SSh that horizontally overlaps a bottom of the first gate trench 1GT, since such a modification would have involved a mere change in the size of a component. In Gardner v. TEC Systems, Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984) (MPEP2144.04.IV.A).
Allowable Subject Matter
Claims 6 and 10 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Reason for indicating allowable subject matter
In re Claim 6: The prior art of record cited by the current office action, alone or in combination, fail to anticipate or render obvious such limitation of claim 6 as: “a buried support shield extension that extends laterally from the support shield”, in combination with limitations of Claims 1 and 5 on which it depends.
In re Claim 10: The prior art of record cited by the current office action, alone or in combination, fail to anticipate or render obvious such limitation of claim 1 as: “a support shield trench is provided in the semiconductor layer structure that extends at least part of the way through the support shield, and conductive material other than silicon carbide is in the support shield trench”, in combination with limitations of Claim 1 on which it depends.
Claims 15-19, 24-27 and 28-29, 32-34 are allowed.
The following is an examiner’s statement of reasons for allowance:
In re Claim 15, prior-art fails to disclose a semiconductor device comprising …/ steps of “a JFET region having the first conductivity type on an upper portion of the drift region, the JFET region having a higher first conductivity type doping concentration than the drift region, a well layer having a second conductivity type on an upper portion of the JFET region, and a support shield having the second conductivity type; and a first gate trench extending into an upper portion of the semiconductor layer structure; wherein a first portion of the JFET region that is in between the first gate trench and the support shield has a width that increases with increasing distance from the well layer.” ‘Therefore, the claimed device differs from prior art devices on this point and there is no evidence it would have been obvious to make this change.
In re Claim 28, prior-art fails to disclose a method of isolating gates in a semiconductor structure comprising “a buried lateral support shield extension having the second conductivity type that extends laterally from the support shield; and a first gate trench extending into an upper portion of the semiconductor layer structure, wherein a sidewall of the support shield extends along a crystallographic axis of the semiconductor layer structure.” Therefore, the claimed device differs from prior art devices on this point and there is no evidence it would have been obvious to make this change.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NIKOLAY K YUSHIN whose telephone number is (571)270-7885. The examiner can normally be reached Monday-Friday (7-7 PST).
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/NIKOLAY K YUSHIN/Primary Examiner, Art Unit 2893
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