DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1-7, 13, 17, 21-23 and 25 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sung et al. (U.S. Publication No. 20240130142 A1; hereinafter Sung) in view of Noh et al. (U.S. Publication No. 2020/0075331 A1; hereinafter Noh)
With respect to claim 1, Sung teaches a semiconductor device, comprising: an active pattern [301] extending in a first direction on a substrate [302]; a plurality of channel layers [306] spaced apart from each other on the active pattern in a direction perpendicular to an upper surface of the substrate and including lower channel layers [306-1] and upper channel layers [306-2] on the lower channel layers (see Figure 3A); an intermediate insulating layer [322-2] between an uppermost lower channel layer among the lower channel layers and a lowermost upper channel layer among the upper channel layers (see Figure 8A); a gate structure [340] intersecting the active pattern, extending in a second direction intersecting the first direction (see Figure 21A-21C), and on the plurality of channel layers; a lower source/drain region [328] on a first side of the gate structure and connected to the lower channel layers; and an upper source/drain region [334] on at least one of the first side or the second side of the gate structure and connected to the upper channel layers (See Figure 27C).
Sung fails to disclose a blocking structure on a second side of the gate structure and connected to the lower channel layers. In the same field of endeavor, Noh teaches a blocking structure [180A] on a second side of the gate structure and connected to the lower channel layers (see Figure 1B). Introduction of a blocking layer prevents short circuits from source/drain regions and prevents unintended epitaxial growth from occurring and isolation between adjacent gate structures while maximizing the space utilized for gate structures (see Noh ¶[0045-0046]). Therefore, it would have been obvious to one of ordinary skill in the art at the time of invention that the combination of references would arrive at the claimed invention.
With respect to claim 2, the combination of Sung and Noh discloses wherein the blocking structure comprises: an insulating liner [181A] extending from a portion of the active pattern on the second side of the gate structure along side surfaces of the lower channel layers; and an insulating gap-fill portion [182A] on the insulating liner (see Noh Figure 2).
With respect to claim 3, the combination of Sung and Noh fails to explicitly disclose wherein the insulating liner has a lower region having a first thickness and an upper region having a second thickness that is smaller than the first thickness, however it has been held that "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955). Therefore, it would have been obvious to one of ordinary skill in the art at the time of invention to optimize the thickness of the insulating liner of Noh based on routine experimentation to provide proper isolation of the adjacent gate structures (see Noh Figure 2).
With respect to claim 4, the combination of Sung and Noh discloses wherein the insulating liner comprises silicon nitride, silicon oxynitride, or silicon carbonitride, and the insulating gap-fill portion comprises silicon oxide (see Noh ¶[0022], ¶[0031], ¶[0049]; requirement for material choice for [180A] is an insulating material and silicon oxide and silicon oxynitride are disclosed within the art as utilized insulating materials).
With respect to claim 5, the combination of Sung and Noh discloses wherein the blocking structure is on a portion of the active pattern on the second side of the gate structure and comprises an insulating gap-fill portion connected to side surfaces of the lower channel layers (See Noh Figure 1B and ¶[0031]).
With respect to claim 6, the combination of Sung and Noh discloses wherein the insulating gap-fill portion comprises silicon nitride, silicon oxynitride, or silicon carbonitride (see Noh ¶[0022] and ¶[0031]; requirement for material choice for [180A] is an insulating material and silicon oxynitride is disclosed and functionally equivalent to the example of silicon oxide within the art as utilized insulating materials).
With respect to claim 7, the combination of Sung and Noh discloses wherein the upper source/drain region is connected to the upper channel layers on the first side of the gate structure, and wherein the blocking structure extends to the upper channel layers on the second side of the gate structure (See Noh Figure 1B).
With respect to claim 13, the combination of Sung and Noh discloses a lower contact [344] connected to the lower source/drain region, and an upper contact [346] connected to the upper source/drain region (See Sung Figure 26E).
With respect to claim 17, Sung discloses a semiconductor device, comprising: an active pattern [301] extending in a first direction on a substrate [302]; first lower channel layers [306-1] on a first region [301-1] of the active pattern and spaced apart from each other in a direction perpendicular to an upper surface of the substrate; second lower channel layers [306-1] on a second region [301-2] of the active pattern and spaced apart from each other in the direction perpendicular to the upper surface of the substrate; third lower channel layers [306-1] on a third region [301-3] of the active pattern and spaced apart from each other in the direction perpendicular to the upper surface of the substrate (See Figure 27A-D and Figure 28); first, second, and third intermediate insulating layers [330] on uppermost lower channel layers of the first, second, and third lower channel layers, respectively; first, second, and third upper channel layers [306-2] stacked and spaced apart from each other on the first, second, and third intermediate insulating layers, respectively; a first gate structure [340] intersecting the first region of the active pattern, extending in a second direction intersecting the first direction and on the first lower channel layers and the first upper channel layers; a second gate structure [340] intersecting the second region of the active pattern, extending in the second direction and on the second lower channel layers and the second upper channel layers; a third gate structure [340] intersecting the third region of the active pattern, extending in the second direction and on the third lower channel layers and the third upper channel layers; a first lower source/drain region [328] between the first and second gate structures and connected to the first and second lower channel layers; a first upper source/drain region [334] between the first and second gate structures and connected to the first and second upper channel layers; Sung fails to disclose a blocking structure between the second and third gate structures, wherein the blocking structure is between the second and third lower channel layers and/or is between the second and third upper channel layers. In the same field of endeavor, Noh teaches a blocking structure [180A] between the second and third gate structures, wherein the blocking structure is between the second and third lower channel layers and/or is between the second and third upper channel layers (see Figure 1B). Introduction of a blocking layer prevents short circuits from source/drain regions and prevents unintended epitaxial growth from occurring and isolation between adjacent gate structures while maximizing the space utilized for gate structures (see Noh ¶[0045-0046]). Therefore, it would have been obvious to one of ordinary skill in the art at the time of invention that the combination of references would arrive at the claimed invention.
With respect to claim 21, the combination of Sung and Noh discloses wherein the blocking structure extends from between the second and third lower channel layers to between the second and third upper channel layers (see Noh Figure 1B).
With respect to claim 22, Sung discloses a semiconductor device, comprising: a first transistor structure on a substrate [302]; and a second transistor structure on the first transistor structure, wherein the first transistor structure comprises: first channel layers [306-1] stacked and spaced apart from each other on the substrate in a vertical direction perpendicular to an upper surface of the substrate; a first gate electrode [340] on the first channel layers; a first source/drain region [328] on a first side of the first gate electrode and connected to first side surfaces of the first channel layers; wherein the second transistor structure comprises: second channel layers [306-2] on the first channel layers and stacked and spaced apart from each other in the vertical direction; a second gate electrode [340] on the second channel layers; first [334] and second [336] upper source/drain regions on first and second sides of the second gate electrode and connected to opposing side surfaces of the second channel layers, respectively (See Figure 27A-27D).
Sung fails to disclose a blocking structure on the first channel layers on a second side of the first gate electrode In the same field of endeavor, Noh teaches a blocking structure [180A] on the first channel layers on a second side of the first gate electrode (see Figure 1B). Introduction of a blocking layer prevents short circuits from source/drain regions and prevents unintended epitaxial growth from occurring and isolation between adjacent gate structures while maximizing the space utilized for gate structures (see Noh ¶[0045-0046]). Therefore, it would have been obvious to one of ordinary skill in the art at the time of invention that the combination of references would arrive at the claimed invention.
With respect to claim 23, the combination of Sung and Noh discloses wherein the blocking structure comprises an insulating liner [181A] extending from an upper surface portion of the substrate on the second side of the first gate electrode along side surfaces of the first channel layers, and an insulating gap-fill portion [182A] on the insulating liner (see Noh Figure 2), and wherein the insulating liner comprises silicon nitride, silicon oxynitride, or silicon carbonitride, and the insulating gap-fill portion comprises silicon oxide (see Noh ¶[0022], ¶[0031], ¶[0049]; requirement for material choice for [180A] is an insulating material and silicon oxide and silicon oxynitride are disclosed within the art as utilized insulating materials).
With respect to claim 25, the combination of Sung and Noh discloses wherein the blocking structure comprises: an insulating gap-fill portion [180A] on an upper surface portion of the substrate on the second side of the first gate electrode and connected to second side surfaces of the first channel layers, wherein the insulating gap-fill portion comprises silicon nitride, silicon oxynitride, or silicon carbonitride (see Noh ¶[0022] and ¶[0031]; requirement for material choice for [180A] is an insulating material and silicon oxynitride is disclosed and functionally equivalent to the example of silicon oxide within the art as utilized insulating materials).
Claim(s) 12, 14-15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sung in view of Noh as applied to claim 1 above, and further in view of Chanemougame et al. (U.S. Patent No. 10,192,819 B1)
With respect to claim 12, the combination of Sung and Noh discloses wherein the semiconductor device further comprises a first interlayer insulating layer [330] on the lower source/drain region and the blocking structure, but fails to disclose a second interlayer insulating layer between the first interlayer insulating layer and the upper source/drain region, and wherein portions of each of the first and second interlayer insulating layer separate the upper source/drain region from the lower source/drain region and the blocking structure. In the same field of endeavor, Chanemougame teaches a second interlayer insulating layer [104] between the first interlayer insulating layer [103] and the upper source/drain region [122a], and wherein portions of each of the first and second interlayer insulating layer separate the upper source/drain region [122a] from the lower source/drain region [112a]. Implementation of a dual layered interlayer insulating layer as taught by Chanemougame allows for increased isolation of source/drain regions of the stacked transistor structure (see Chanemougame Column 14, lines 24-35). Therefore, it would have been obvious to one of ordinary skill in the art at the time of invention that the combination of references would arrive at the claimed invention.
With respect to claim 14, the combination of Sung and Noh fails to disclose wherein the lower contact comprises a first horizontal contact portion connected to the lower source/drain region and extending in a horizontal direction parallel to the upper surface of the substrate, and a first vertical contact portion connected to the first horizontal contact portion and extending in the direction perpendicular to the upper surface of the substrate. In the same field of endeavor, Chanemougame teaches wherein the lower contact [162] comprises a first horizontal contact portion connected to the lower source/drain region and extending in a horizontal direction parallel to the upper surface of the substrate, and a first vertical contact portion connected to the first horizontal contact portion and extending in the direction perpendicular to the upper surface of the substrate (See Figure 15D). Implementation of a contact structure as taught by Chanemougame allows for reduced resistance within the contact structure and allow for size scaling and reducing the number of metal tracks required (see Column 8, line 65- Column 9, line 4 and Column 15, line 4-16). Therefore, it would have been obvious to one of ordinary skill in the art at the time of invention that the combination of references would arrive at the claimed invention
With respect to claim 15, the combination of Sung, Noh, and Chanemougame discloses wherein a first buried electrode [171] in the substrate, wherein the first vertical contact portion extends toward the substrate and is connected to the first buried electrode (see Chanemougame Figure 1B).
Claim(s) 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sung in view of Noh as applied to claim 13 above, and further in view of Peng et al. (U.S. Publication No. 2022/0123023 A1; hereinafter Peng).
With respect to claim 16, the combination of Sung and Noh discloses wherein the upper contact comprises a second horizontal contact portion [348] connected to the upper source/drain region and extending in a horizontal direction parallel to the upper surface of the substrate (see Figure 26D), but fails to disclose a second buried electrode buried in the substrate and a second vertical contact portion connecting the second horizontal contact portion to the second buried electrode. In the same field of endeavor, Peng teaches a second buried electrode [134] buried in the substrate and a second vertical contact portion [164] connecting the second horizontal contact portion to the second buried electrode (See Figure 2D). Implementing a second buried electrode and contact as taught by Peng within the device of Sung and Noh allows for efficient backside interconnection rather than isolating all connections to frontside (See Peng ¶[0060]). Therefore, it would have been obvious to one of ordinary skill in the art at the time of invention that the combination of references would arrive at the claimed invention.
Allowable Subject Matter
Claims 18-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
With respect to claims 18-19, none of the prior art teaches or suggests, alone or in combination, wherein the blocking structure comprises a lower blocking structure between the second and third lower channel layers, and wherein the semiconductor device further comprises a second upper source/drain region connected to the second and third upper channel layers between the second and third gate structures.
With respect to claim 20, none of the prior art teaches or suggests, alone or in combination, wherein the blocking structure comprises an upper blocking structure between the second and third upper channel layers, and wherein the semiconductor device further comprises a second lower source/drain region connected to the second and third lower channel layers between the second and third gate structures.
Conclusion
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/JONATHAN HAN/Primary Examiner, Art Unit 2818