DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Election/Restrictions
Applicant's election with traverse of Species I (claims 1-6 and 13-18) in the reply filed on March 2nd, 2026 is acknowledged. The traversal is on the ground(s) that the Office fails to demonstrate the serious burden on examining all species. This is not found persuasive because even though pending claims only directed to generic four- layer semiconductor device, but there are total of 5 different species disclosed in the applicant’s drawing and Applicant can amend claims direct to any of these drawings which would create serious burden for searching all of these different structures of species. These different structures would require different field of search, different search queries and different prior art for rejections.
The requirement is still deemed proper and is therefore made FINAL.
Claims 7-12 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Species, there being no allowable generic or linking claim.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claim 17 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
Claim 17 recites the limitation “the buried third and/or fourth well” in lines 1-2. There is insufficient antecedent basis for this limitation in the claim.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-6, 14-16 and 18 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by OTSUBO et al. (Pub. No.: US 2020/0403072 A1), hereinafter as OTSUBO.
Regarding claim 1, OTSUBO discloses a four-layer semiconductor device in Fig. 2, comprising: a semiconductor substrate of a first charge type (combination of layer 3, layer 1 and substrate 5 of p-type) (see [0030-0031]); an epitaxial layer (layer 2) arranged on the semiconductor substrate in which a first region of a second charge type (device region R1 of n type) and a second region of the second charge type (device region R2) are formed (see [0027]); a first contact region of the first charge type (p+ drain region 16d) formed in the first region, and a first device terminal (metal plug 32/drain electrode 35d) electrically connected to the first contact region (see [0038] and [0048]); a second contact region of the second charge type (n+ contact region 22) formed in the second region, and a second device terminal (metal plug 32/drain electrode 36d) electrically connected to the second contact region (see [0042] and [0048]); a third contact region of the second charge type (n+ drain region 12d) formed in the first region, wherein the first device terminal is electrically connected to the third contact region (when the devices in operation, drain electrode 35d connecting to drain electrode 34d and connecting to drain region 12d in a complete circuit) (see [0037]); wherein the four-layer semiconductor device further comprises an electrical insulation (insulating film 58 of isolation structure 8B) extending at least partially inside the epitaxial layer that prevents a current from flowing between the first device terminal and the second device terminal that does not at least partially flow through the semiconductor substrate (insulating film 58 extending into layer 1 and preventing currenting from region R1 flowing into region R2) (see Fig. 3, [0027] and [0055-0056]); and wherein the electrical insulation extends through the epitaxial layer and into the semiconductor substrate (insulating film 58 extending from layer 2 into layer 1) (see Fig. 2).
Regarding claim 2, OTSUDO discloses the four-layer semiconductor device according to claim 1, wherein the semiconductor substrate has a dopant concentration that lies in the range between 1016 and 1021 #/cm3 (see concentrations of layers 1, 3 and substrate 5) (see [0029-0032]).
Regarding claim 3, OTSUDO discloses the four-layer semiconductor device according to claim 1, wherein the electrical insulation comprises a first insulation (left portion of insulating layer 58) and a second insulation (right portion of insulating layer 58) separated from the first insulation, wherein the first insulation is arranged between the first region and the second insulation (between device regions R1 and R2), and wherein the second insulation is arranged between the second region and the first insulation (see Figs. 2-3).
Regarding claim 4, OTSUDO discloses the four-layer semiconductor device according to claim 3, wherein the electrical insulation, or the first and second insulation, comprises a deep trench isolation (see Figs. 4E-4F).
Regarding claim 5, OTSUDO discloses the four-layer semiconductor device according to claim 1, wherein the first region and the second region form a contiguous region (see Fig. 2).
Regarding claim 6, OTSUDO discloses the four-layer semiconductor device according to claim 1, further comprising a fourth contact region of the first charge type (p-type well 25) formed in the second region, wherein the second device terminal is electrically connected to the fourth contact region (drain electrode 36d electrically connecting to p-type well 25 through source electrode 36s in a circuit when the device in operation) (see Fig. 2 and [0042], [0048]).
Regarding claim 14, OTSUDO discloses the four-layer semiconductor device according to claim 1, wherein the four-layer semiconductor device is a silicon-controlled rectifier (SCR) (Fig. 2 of OTSUDO recites all limitation of claim 1 and can be utilized to have function of silicon-controlled rectifier as claimed).
Regarding claim 15, OTSUDO discloses An electrostatic discharge (ESD) protection device for enabling a discharge current to flow from a node to be protected to a reference node (Fig. 2 of OTSUDO recites all limitation of claim 1 and can function as ESD device), wherein the reference node is ground, wherein the ESD protection device comprises the four-layer semiconductor device as defined in claim 1, wherein the first diode terminal is electrically connected to the node to be protected, and wherein the second diode terminal is electrically connected to the reference node (Fig. 2 recites all limitation as claimed and therefore can have all functions as claimed here).
Regarding claim 16, OTSUDO discloses the four-layer semiconductor device according to claim 1, wherein the substrate has a dopant concentration (concentration of layers 1, 3 and substrate 5 meets the required range of the dopant concentration as shown in the rejections of claim 2) that is chosen so that with respect to a triggering voltage Vt and holding voltage Vh of the four-layer semiconductor device:(Vt-Vh)/Vt is less than 0.7; and/or Vh> 1.5V (would meet this requirement because having the same dopant concentration of the applicant’s device).
Regarding claim 18, OTSUDO discloses an electrostatic discharge (ESD) protection device for enabling a discharge current to flow from a node to be protected to a reference node (Fig. 2 of OTSUDO recites all limitation of claim 1 and can function as ESD device), wherein the reference node is ground, wherein the ESD protection device comprises the four-layer semiconductor device as defined in claim 2, wherein the first diode terminal is electrically connected to the node to be protected, and wherein the second diode terminal is electrically connected to the reference node (Fig. 2 recites all limitation as claimed and therefore can have all functions as claimed here).
Allowable Subject Matter
Claim 13 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is an examiner's statement of reasons for the indication of allowable subject matter: The cited art, whether taken singularly or in combination, especially when all limitations are considered within the claimed specific combination, fails to disclose or suggest the claimed invention having:
wherein the first region and second region has a dopant concentration that is chosen so that with respect to a triggering voltage Vt and holding voltage Vh of the four-layer semiconductor device:(Vt-Vh)Nt is less than 0.7; and/or Vh>1.5V.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CUONG B NGUYEN whose telephone number is (571)270-1509 (Email: CuongB.Nguyen@uspto.gov). The examiner can normally be reached Monday-Friday, 8:30 AM-5:00 PM Eastern Standard Time.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Steven H. Loke can be reached on (571) 272-1657. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/CUONG B NGUYEN/Primary Examiner, Art Unit 2818