Prosecution Insights
Last updated: May 29, 2026
Application No. 18/482,201

Method of Manufacturing a Semiconductor Package, Such Semiconductor Package as well as an Electronic System Comprising a PCB Element and at Least Such Semiconductor Package

Non-Final OA §102§103§112
Filed
Oct 06, 2023
Priority
Oct 06, 2022 — EU 22199970.9
Examiner
HALL, VICTORIA KATHLEEN
Art Unit
2897
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Nexperia B V
OA Round
1 (Non-Final)
84%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 84% — above average
84%
Career Allowance Rate
687 granted / 821 resolved
+15.7% vs TC avg
Strong +19% interview lift
Without
With
+19.1%
Interview Lift
resolved cases with interview
Typical timeline
2y 4m
Avg Prosecution
21 currently pending
Career history
852
Total Applications
across all art units

Statute-Specific Performance

§101
0.7%
-39.3% vs TC avg
§103
64.3%
+24.3% vs TC avg
§102
4.5%
-35.5% vs TC avg
§112
18.5%
-21.5% vs TC avg
Black line = Tech Center average estimate • Based on career data from 821 resolved cases

Office Action

§102 §103 §112
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Priority Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55. Specification The disclosure is objected to because of the following informalities: Page 3, paragraph 6, line 3 of step (c): Change “at least one an opening” to “at least one opening”. Compare with step (e), line 2. Page 6, paragraph 26, line 2: Change “it manufactured” to “it is manufactured”. Page 9, paragraph 42, line 6: After “solder pads”, add “by soldering alloy 14”. There is no other reference to soldering alloy 14 in the main text of the disclosure, and sometimes the Office’s publication’s staff objects to the listing of reference numbers at the end of a specification. Adding this reference here will ensure that the soldering alloy 14 is mentioned in the main text of the disclosure. Appropriate correction is required. Claim Objections Claims 1-18 are objected to because of the following informalities: Claim 1, line 4: Add “conductive” before “terminal”. Claim 1, line 6: Add “conductive” before “terminal”. Claim 1, line 9: Add “conductive” before “terminal”. Claim 1, line 10: Add “conductive” before “terminal”. Claim 1, line 11: Add “conductive” before “terminal”. Also, please provide antecedent basis for “the encapsulant”. Claim 1, line 17: Add “conductive” before “terminal”. Claims 2-9 and 11-17 stand objected to for depending from objected-to base claim 1. Claim 2, line 2: Add “conductive” before “terminal”. Claims 11-16 are objected to for depending from objected-to base claim 2. Claim 4, line 2: Change “the encapsulating process” to “step c)”. Claims 8 and 9, line 3: Is there a difference between a lead terminal (claim 8) and a terminal (claim 9)? If not, please make the term consistent between the two claims. Claim 10, line 2: Please provide antecedent basis for “the encapsulant”. Claim 18 is objected to for depending from objected-to base claim 10. Claim 12, line 2: Please provide antecedent basis for “the encapsulating process”. Claim 16, lines 2-3: Claim 16 refers to “a lead terminal”. See the note with respect to claims 8 and 9, and if there is no difference between a terminal and a lead terminal, use a term consistent with claims 8 and 9. Claim 17, line 2: Please provide antecedent basis for “the encapsulating process”. Appropriate correction is required. Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claims 1-18 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Regarding claim 1: This claim, directed to a method, defines a semiconductor package, followed by the steps for making the package. Several inconsistencies arise in the claim which result in confusing language. Specifically, the claim requires the following: [a] method of manufacturing a semiconductor package having at least one semiconductor die connected with at least one conductive terminal, wherein the semiconductor package has an upper side and a bottom side and wherein the at least one terminal is located at least partially on the bottom side, the method comprising the steps of: a) providing a lead frame having a plurality of terminals for establishing external electrical connections; b) attaching electrically and mechanically the at least one semiconductor die to the at least one terminal of the lead frame located at least partially on the bottom side; c) encapsulating the semiconductor die and the plurality of terminals so that at least a portion of at least one terminal is exposed and the encapsulant is provided on the bottom side with at least one opening that at least partially is exposing the semiconductor die; d) cleaning the bottom side of the semiconductor package; e) partially plating a conductive layer on a bottom side of the encapsulant, electrically connecting the semiconductor die via the at least one opening with the portion of the at least one terminal exposed from the encapsulant and external to the semiconductor package, and; f) singulating the semiconductor package from the lead frame. (emphasis added). First, the reference to the “at least one conductive terminal” and the “plurality of terminals” is vague because the language is not clear that the “at least one conductive terminal” is one of terminals of the “plurality of terminals”. Second, the claim refers to the semiconductor package having “at least one semiconductor die” in some places, and to “the semiconductor die” in other places. The inconsistency in the language is confusing. Third, step b) refers to “the bottom side”. This appears to refer to the semiconductor package, but at this stage, the semiconductor package has not been made. The packaging step is step c), which also refers to “the bottom side”, although given the context of the reference, the claim is unclear which “bottom side” is being referred to. Furthermore, step b) is unclear where “the bottom side” is, if the semiconductor package is not present. Step e) also refers to “a bottom side”, this time of the encapsulant, but the difference is not clear between the bottom side of the encapsulant and the bottom side of the semiconductor package, vs. the bottom side referred to in step b). Fourth, step c) should clarify that the semiconductor package is formed with the encapsulation step, because step d) refers to the semiconductor package as being cleaned. Lastly, antecedent basis has not been provided for “the encapsulant” in step c). Because the language is vague and confusing, and antecedent basis is missing, claim 1 is rejected as indefinite. Claims 2-9 and 11-17 are rejected for depending from rejected base claim 1. Regarding claim 2, which depends from claim 1: As with claim 1, claim 2 also refers to “the semiconductor die” instead of “the at least one semiconductor die”. Because of the difference in language, claim 2 is confusing, and rejected as indefinite. Claims 11-16 are rejected for depending from rejected base claim 2. Regarding claim 3, which depends from claim 1: This claim is rejected on two bases. First, claim 3, line 1 refers to “the semiconductor die” as opposed to the “at least one semiconductor die” of claim 1. The use of the different terms is confusing. For this reason, claim 3 is rejected as indefinite. Second, claim 3, line 2, also refers to “the bottom side”, which given the context is likely the bottom side of the semiconductor package, but if changes are made to claim 1, the specific “bottom side” should be made clear. Otherwise, claim 3 is rejected for being vague. Claim 17 is rejected for depending from rejected base claim 3. Regarding claim 4, which depends from claim 1: This claim is rejected on two bases. First, claim 4 refers to “the encapsulation process”, but antecedent basis has not been provided for the encapsulation process. Because antecedent basis is absent, claim 4 is rejected as indefinite. Second, claim 1, line 12, (step c)) refers to “at least one opening”, but claim 4 refers to “the opening”. The use of different terms is confusing. For this reason, claim 4 is rejected as indefinite. Regarding claim 5, which depends from claim 1: As with claim 4, claim 1, line 12, (step c)) refers to “at least one opening”, but claim 5 refers to “the opening”. The use of different terms is confusing. For this reason, claim 5 is rejected as indefinite. Regarding claim 10: This claim is rejected on two bases. First, antecedent basis has not been provided for “the encapsulant” in line 2. Because antecedent basis is missing, claim 10 is rejected as indefinite. Second, claim 10 refers to the semiconductor package having “at least one semiconductor die” in line 1, and then to “the semiconductor die” in line 4. The inconsistency in the language is confusing. For this reason, claim 10 is rejected as indefinite. Claim 18 is rejected for depending from rejected base claim 10. Regarding claim 11, which depends from claim 2: This claim is rejected on two bases. First, claim 11, line 1 refers to “the semiconductor die” as opposed to the “at least one semiconductor die” of claim 1. The use of the different terms is confusing. For this reason, claim 11 is rejected as indefinite. Second, claim 11, line 2, also refers to “the bottom side”, which given the context is likely the bottom side of the semiconductor package, but if changes are made to claim 1, the specific “bottom side” should be made clear. Otherwise, claim 11 is rejected for being vague. Regarding claim 12, which depends from claim 2: This claim is rejected on two bases. First, claim 12 refers to “the encapsulation process”, but antecedent basis has not been provided for the encapsulation process. Because antecedent basis is absent, claim 12 is rejected as indefinite. Second, claim 1, line 12, (step c)) refers to “at least one opening”, but claim 12 refers to “the opening”. The use of different terms is confusing. For this reason, claim 12 is rejected as indefinite. Regarding claim 13, which depends from claim 2: As with claim 12, claim 1, line 12, (step c)) refers to “at least one opening”, but claim 13 refers to “the opening”. The use of different terms is confusing. For this reason, claim 13 is rejected as indefinite. Regarding claim 17, which depends from claim 3: This claim is rejected on two bases. First, claim 17 refers to “the encapsulation process”, but antecedent basis has not been provided for the encapsulation process. Because antecedent basis is absent, claim 17 is rejected as indefinite. Second, claim 1, line 12, (step c)) refers to “at least one opening”, but claim 17 refers to “the opening”. The use of different terms is confusing. For this reason, claim 17 is rejected as indefinite. Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claim 10 is rejected under 35 U.S.C. 102(a)(1)/(a)(2) as being anticipated by Bowers, U.S. Pat. Pub. No. 2022/0115301, Figures 15A-15D. PNG media_image1.png 323 690 media_image1.png Greyscale PNG media_image2.png 268 700 media_image2.png Greyscale PNG media_image3.png 410 700 media_image3.png Greyscale Regarding claim 10: Bowers Figures 15A-15D discloses a semiconductor package (1-100) comprising at least one semiconductor die (120) connected with at least one first conductive terminal (1-122) surrounded by the encapsulant (130), wherein the semiconductor package (1-100) has an upper side and a bottom side, and further comprising a conductive plate (1-113) on the bottom side connecting the semiconductor die (120) with at least one second conductive terminal (1-112). Bowers specification ¶¶ 168-170, ¶ 53 (describing electronic component (120) as one or more dies, chips, or packages, and providing examples), 29 (reference numbers in different figures denote the same elements). Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Bowers, and further in view of Talledo, U.S. Pat. Pub. No. 2016/0183369, Figure 2B. PNG media_image4.png 341 631 media_image4.png Greyscale Regarding claim 18: Bowers Figures 15A-15D discloses at least one semiconductor package according to claim 10, as discussed above in the Section 102 rejection. Bowers Figures 15A-15D is silent as its connection to a PCB. Talledo Figure 2B, directed to similar subject matter, discloses an electronic system comprising a PCB element (46) provided with solder pads (48) and at least one semiconductor package (10), with the at least one semiconductor package (10) being attached with the at least one first and at least one second terminals (left, right (18)) to the PCB element (46) via the solder pads (48). Talledo specification ¶¶ 23-29. One having ordinary skill in the art at a time before the effective filing date would be motivated to modify Talledo to substitute the Bowers package for the Talledo package because the modification would have involved the substitution of an equivalent known for the same purpose. To the extent that solder balls (48) would not be considered to be solder pads, when the solder balls (48) are combined with solder material (32) and joined, the result is the same as or similar to a solder pad, and thus the requirement for a solder pad would be an obvious variant over the prior art. Allowable Subject Matter Claims 1-9 and 11-17 would be allowable if rewritten or amended to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action, and if the claim objections were addressed. The following is a statement of reasons for the indication of allowable subject matter: With regard to claim 1: The claim has been found allowable because the prior art of record does not disclose “c) encapsulating the semiconductor die and the plurality of terminals so that at least a portion of at least one terminal is exposed and the encapsulant is provided on the bottom side with at least one opening that at least partially is exposing the semiconductor die; d) cleaning the bottom side of the semiconductor package; e) partially plating a conductive layer on a bottom side of the encapsulant, electrically connecting the semiconductor die via the at least one opening with the portion of the at least one terminal exposed from the encapsulant and external to the semiconductor package,”, in combination with the remaining limitations of the claim. With regard to claims 2-9 and 11-17: The claims have been found allowable due to their dependency from claim 1 above. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to VICTORIA KATHLEEN HALL whose telephone number is (571)270-7567. The examiner can normally be reached Monday-Friday, 8 a.m.-5 p.m. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Fernando Toledo can be reached at 571-272-1867. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /Victoria K. Hall/Primary Examiner, Art Unit 2897
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Prosecution Timeline

Oct 06, 2023
Application Filed
Jan 20, 2026
Non-Final Rejection mailed — §102, §103, §112
Apr 20, 2026
Response Filed

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
84%
Grant Probability
99%
With Interview (+19.1%)
2y 4m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 821 resolved cases by this examiner. Grant probability derived from career allowance rate.

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