Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Status of Claims
Applicant's amendment of claim 1 and cancellation of claims 12-20 in “Claims - 07/09/2026” with “Amendment/Req. Reconsideration-After Non-Final Reject - 07/09/2026”, have been acknowledged by Examiner.
This office action considers claims 1-11 pending for prosecution.
Response to Arguments
1. Applicant's arguments filed in the “Applicant Arguments/Remarks Made in an Amendment” on 07/09/2026 have been fully considered, but they are not persuasive, because of the following: the Applicant's amendment of claim 1 necessitated the shift in new grounds of rejection detailed in sections below. The shift in grounds of rejection renders the Applicant's arguments moot.
Please see the analysis of rejection for claims below.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Notes: when present, semicolon separated fields within the parenthesis (; ;) represent, for example, as (30A; Fig 2B; [0128]) = (element 30A; Figure No. 2B; Paragraph No. [0128]). For brevity, the texts “Element”, “Figure No.” and “Paragraph No.” shall be excluded, though; additional clarification notes may be added within each field. The number of fields may be fewer or more than three indicated above. These conventions are used throughout this document.
2. Claims 1-6 and 8-11 is rejected under 35 U.S.C.103 as being unpatentable over Gauthier, JR. et al (US 20150348960 A1; hereinafter Gauthier, JR.), in view of Bonilla et al. (US 20120326269 A1; hereinafter Bonilla).
Regarding claim 1, Gauthier, JR. teaches a semiconductor structure (see the entire document, specifically Fig. 1+; [0008+], and as cited below), comprising:
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an electronic fuse via (44; Figs. 1 ,2; [0021]) having a positive tapered shape extending from a back-end-of-the-line interconnect (46; see Fig. 2; see [0021]) to a backside power delivery network (see Figs. 1, 2; see [0012, 0016-0020]);
wherein the positive tapered shape (44; Figs. 1 ,2; [0021]) of the electronic fuse via (44; Figs. 1 ,2; [0021]) comprises an upper portion (upper portion of 44; Figs. 1 ,2; [0021]) disposed in an interlevel dielectric layer (50; Figs. 1 ,2; [0021]; see Annotated Fig 2, above; labeled as Interlevel), and a lower portion (lower portion of 44; Figs. 1 ,2; [0021]) disposed in (see below for “a shallow trench isolation”) region (see Annotated Fig 2, above; labeled as Region); and
wherein the electronic fuse via (44; Figs. 1 ,2; [0021]) comprises a conductive material.
As noted above, Gauthier, JR. does not expressly disclose “wherein the positive tapered shape of the electronic fuse via comprises an upper portion disposed in an interlevel dielectric layer, and a lower portion disposed in a shallow trench isolation region”, though Gauthier, JR. does teach a lower portion (lower portion of 44; Figs. 1 ,2; [0021]) disposed in a region (see Annotated Fig 2, above; labeled as Region). Yet, Gauthier, JR. seems to be silent on the material of the Region.
However, in the analogous art, Bonilla teaches e-fuse structures in back end of the line (BEOL) interconnects ([0001]), wherein (Fig. 1+; [0009+]) metal (80; Fig. 12 in view o Figs. 10-11; [0035]) is deposited in the vias (36a) and (46), where a via in (36a) has an upper portion insulator layer (25; [0037]) and bottom portion in cap layer (20; [0037]), where cap layer (20; [0037, 0018]) comprises of a dielectric material.
It would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to modify Gauthier, JR.’s material of the Region in view of Bonilla’s the dielectric material of the cap layer, and thereby, modified Gauthier, JR.’s (by Bonilla) device will have wherein the positive tapered shape (Gauthier, JR. 44; Figs. 1 ,2; [0021]) of the electronic fuse via (Gauthier, JR. 44; Figs. 1 ,2; [0021]) comprises an upper portion (Gauthier, JR. upper portion of 44; Figs. 1 ,2; [0021]) disposed in an interlevel dielectric layer (Gauthier, JR. 50; Figs. 1 ,2; [0021]; see Annotated Fig 2, above; labeled as Interlevel), and a lower portion (Gauthier, JR. lower portion of 44; Figs. 1 ,2; [0021]) disposed in a shallow trench isolation region (Gauthier, JR. see Annotated Fig 2, above; labeled as Region in view of material of Bonilla 20; [0037, 0018]; a dielectric material; see also [0045] of the instant invention where it states that the “STI region 108 comprises a dielectric material”. Therefore, it is construed that the Gauthier, JR.’s Region in view of the dielectric material of Bonilla 20; [0037, 0018] is a shallow trench isolation region).
The ordinary artisan would have been motivated to modify Gauthier, JR. in the manner set forth above, at least, because this inclusion provides a dielectric material that surrounds the via (Bonilla [0037, 0018]), which helps increase the insulation of the via and helps further protect the device.
Regarding claim 2, modified Gauthier, JR. (by Bonilla) teaches all of the features of claim 1.
Gauthier, JR. further teaches wherein the positive tapered shape of the electronic fuse via (44; Figs. 1 ,2; [0021]) comprises an upper portion connected to the back-end-of-the-line interconnect (46; see Fig. 2; see [0021]) having a first width and lower portion connected to the backside power delivery network (see Figs. 1, 2; see [0012, 0016-0020]) having a second width less than the first width.
Regarding claim 3, modified Gauthier, JR. (by Bonilla) teaches all of the features of claim 1.
Gauthier, JR. further teaches wherein the electronic fuse via (44; Figs. 1 ,2; [0021]) is connected to the back-end-of-the-line interconnect (46; see Fig. 2; see [0021]) through a first conductive metal line of a metallization layer (see [0021], where it states that “the representative efuse 40a that includes metallic features contained in an interconnect level of a back-end-of-line (BEOL) interconnect structure and/or a middle-end-of-line (MEOL) interconnect structures”), and the electronic fuse via (44; Figs. 1 ,2; [0021]) is connected to the backside power delivery network (see Figs. 1, 2; see [0012, 0016-0020]) through a first backside middle-of-the-line contact (42; Figs. 1 ,2; [0021]).
Regarding claim 4, modified Gauthier, JR. (by Bonilla) teaches all of the features of claim 3.
Gauthier, JR. further teaches wherein the first backside middle-of-the-line contact (42; Figs. 1 ,2; [0021]) is connected to the backside power delivery network (see Figs. 1, 2; see [0012, 0016-0020]) through a first backside power rail (see Figs. 1, 2; see [0012, 0016-0022]).
Regarding claim 5, modified Gauthier, JR. (by Bonilla) teaches all of the features of claim 2.
Gauthier, JR. further teaches wherein the upper portion of the electronic fuse via (44; Figs. 1 ,2; [0021]) is connected to the back-end-of-the-line interconnect through a conductive metal line of a metallization layer (see [0021], where it states that “the representative efuse 40a that includes metallic features contained in an interconnect level of a back-end-of-line (BEOL) interconnect structure and/or a middle-end-of-line (MEOL) interconnect structures”), and the lower portion of the electronic fuse (44; Figs. 1 ,2; [0021]) via is connected to the backside power delivery network (see Figs. 1, 2; see [0012, 0016-0020]) through a backside middle-of-the-line contact (42; Figs. 1 ,2; [0021]).
Regarding claim 6, modified Gauthier, JR. (by Bonilla) teaches all of the features of claim 5.
Gauthier, JR. further teaches wherein the backside middle-of-the-line contact (42; Figs. 1 ,2; [0021]) is connected to the backside power delivery network (see Figs. 1, 2; see [0012, 0016-0020]) through a backside power rail (see Figs. 1, 2; see [0012, 0016-0022]).
Regarding claim 8, modified Gauthier, JR. (by Bonilla) teaches all of the features of claim 3.
Gauthier, JR. further comprising another electronic fuse via (see Figs. 1, 2; see [0021], where it states that “each of the efuses 40a-40 n may have a construction as shown by the representative efuse 40a”) having a positive tapered shape (see Figs. 1, 2; see [0021]) extending from the back-end-of-the-line interconnect (46; see Fig. 2; see [0021]) to the backside power delivery network (see Figs. 1, 2; see [0012, 0016-0020]); wherein the other electronic fuse via (see Figs. 1, 2; see [0021]) comprises another conductive material.
Regarding claim 9, modified Gauthier, JR. (by Bonilla) teaches all of the features of claim 8.
Gauthier, JR. further teaches wherein the other electronic fuse via (see Figs. 1, 2; see [0021], where it states that “each of the efuses 40a-40 n may have a construction as shown by the representative efuse 40a”) is connected to the back-end-of-the-line interconnect through a second conductive metal line of the metallization layer (see [0021], where it states that “the representative efuse 40a that includes metallic features contained in an interconnect level of a back-end-of-line (BEOL) interconnect structure and/or a middle-end-of-line (MEOL) interconnect structures”), and the other electronic fuse via (see Figs. 1, 2; see [0021], where it states that “each of the efuses 40a-40 n may have a construction as shown by the representative efuse 40a”) is connected to the backside power delivery network (see Figs. 1, 2; see [0012, 0016-0020]) through a second backside middle-of-the-line contact (42; Figs. 1 ,2; [0021]).
Regarding claim 10, modified Gauthier, JR. (by Bonilla) teaches all of the features of claim 1.
Gauthier, JR. further teaches wherein the electronic fuse via (44; Figs. 1 ,2; [0021]) is co-integrated with a logic device (see [0026]; see also [0023-0025]) through the backside power delivery network (see Figs. 1, 2; see [0012, 0016-0020]).
Regarding claim 11, modified Gauthier, JR. (by Bonilla) teaches all of the features of claim 9.
Gauthier, JR. further teaches wherein the second backside middle-of-the-line contact (42; Figs. 1 ,2; [0021]) is connected to the backside power delivery network (see Figs. 1, 2; see [0012, 0016-0020]) through a second backside power rail (see Figs. 1, 2; see [0012, 0016-0020]).
3. Claim 7 is rejected under 35 U.S.C.103 as being unpatentable over Gauthier, JR. et al (US 20150348960 A1; hereinafter Gauthier, JR.), in view of Bonilla et al. (US 20120326269 A1; hereinafter Bonilla), in view of Jacob et al. (US 20170092583 A1; hereinafter Jacob).
Regarding claim 7, modified Gauthier, JR. (by Bonilla) teaches all of the features of claim 1.
Gauthier, JR. further teaches wherein the conductive material (44; Figs. 1 ,2; [0021]) (see below for “comprises a poly-Si, or silicided poly-Si material”).
As noted above, Gauthier, JR. does not expressly disclose “wherein the conductive material comprises a poly-Si, or silicided poly-Si material”.
However, in the analogous art, Jacob teaches programmable via devices having via links which include metal and semiconductor portions ([0001]), wherein (Fig. 1+; [0090+]) a silicide based via link, which may be integrated into BEOL processes, with via links being disposed in vias between metal layers ([0058]), where a via link (210; Fig. 2C; [0036]) comprising of a semiconductor portion that includes a polycrystalline material, such as polycrystalline silicon (polysilicon), where the semiconductor portion may be heavily doped with either p-type or n-type dopants to increase its conductivity, where the via link may further comprise a silicide based via links may be formed by depositing polysilicon onto refractory metal filled via, followed by annealing, for example, to form junctions ([0058]).
It would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to modify Gauthier, JR.’s via material in view of Jacob’s silicide based via link comprising of polysilicon, and thereby, modified Gauthier, JR.’s (by Bonilla and Jacob) device will have wherein the conductive material (Gauthier, JR.44; Figs. 1 ,2; [0021] in view of material of Jacob [0036, 0058]) comprises a poly-Si, or silicided poly-Si material (in view of material of Jacob [0036, 0058]).
The ordinary artisan would have been motivated to modify Gauthier, JR. in the manner set forth above, at least, because this inclusion provides silicide based via link comprising of polysilicon that has increased conductivity and upon passing current through the via link, migration, such as electromigration may occur (Jacob [0036, 0058]), which helps increase the functionality of the device.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Omar Mojaddedi whose telephone number is 313-446-6582. The examiner can normally be reached on Monday – Friday, 8:00 a.m. to 4:00 p.m..
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/OMAR F MOJADDEDI/Examiner, Art Unit 2898
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