DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments filed 02/03/2026 have been fully considered but they are not persuasive.
First of all, Applicant argued that “neither reference teaches storing a refresh control code corresponding to a completed self-refresh operation and incrementing that stored code". The Examiner respectfully disagrees for the following reasons: Jang explicitly discloses storing refresh parameters in mode registers (e.g., refresh time register 192, fail bit mode register 194) and using them to control refresh timing (FIGS. 5, 6A, 6B, and ¶[0052]-[0057]). The refresh control logic adjusts the refresh clock frequency based on these stored values. And Kang teaches periodic adjustment of the self-refresh cycle based on error detection (FIGS. 4-5, ¶[0026]-[0029]). When no errors are detected in monitoring bits, the refresh cycle is increased. This inherently involves a stored or remembered value (the current refresh cycle length) that is modified over time. Therefore, a skilled artisan would recognize that implementing Kang's feedback loop in a practical circuit would naturally require storing the current refresh cycle value (e.g., in a register) and incrementing it when conditions permit, which is exactly the "addition code" concept. This is a routine design choice, not an inventive leap.
Secondly, Applicant argued that “the cited art relies on refresh determinations based on contemporaneous conditions, without the claimed reuse and incremental modification of a prior-cycle control code". The Examiner respectfully disagrees for the following reasons: Kang's method is inherently iterative: after setting an initial refresh cycle, it waits a predetermined time (Δt), rechecks error flags, and adjusts the cycle again (see FIG. 5, steps S160, S240-S256). This is a cycle-to-cycle modification based on prior results. Besides, the "addition code" in the claim is simply a way to quantify the increment. Kang's teaching that "the self-refresh cycle tREF increases" when bits are normal (¶[0026], FIG. 4 step S154) directly implies an incremental increase from one cycle to the next. The use of a stored code to track this increment is a conventional implementation detail.
Lastly, Applicant argued that "the present claim language requires ... combining the temperature code with a stored and incremented addition code". The Examiner respectfully disagrees for the following reasons: Jang explicitly combines temperature information with error information to determine refresh timing (FIGS. 9-12, ¶[0080]-[0097]). The refresh clock controller (273a, 273b, 273c) adjusts the refresh clock frequency based on both temperature and error flags. Therefore, it would be obvious to use Kang's error-based adjustment scheme within Jang's temperature-compensated framework. The "combination" of temperature code and addition code is merely a straightforward integration of two known parameters to set a variable refresh period, which is a common design practice.
Thus, the applicant's arguments fail to identify any patentable distinction. The claimed stepwise modification using a stored and incremented addition code is an obvious implementation of the adaptive refresh cycles taught by Kang and Jang. The rejection under 35 U.S.C. § 103 is maintained.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-20 are rejected under 35 U.S.C. 103 as being unpatentable over Jang et al (US2019/0139596 A1) (hereinafter D1) and further in view of Kang et al (US2007/0133315 A1) (hereinafter D2).
Claim 1: D1 teaches a self-refresh method of a semiconductor memory device, comprising:
generating a temperature code (e.g. temperature information) indicative of a temperature of the semiconductor memory device (e.g. Temperature sensor 295 senses internal driving temperature and provides current temperature information C_temp to refresh control logic 270 (FIG. 9, ¶[0081], [0093]));
generating a first error flag indicative of any data errors in a memory area of the semiconductor memory device (e.g. Error correction circuit 265 provides error information ECC_info (e.g., fail bit count) to refresh control logic; fail bit mode register 194 stores acceptable fail bit count (FIG. 9-12, ¶[0080], [0082]));
performing a first self-refresh operation for the memory area within a first refresh period based on the temperature code and the first error flag (e.g. Refresh control logic 270 determines refresh time tRC/optimal refresh time tRC_opt with reference to access scenario information, temperature information C_temp, and error information ECC_info; performs self-refresh at calculated intervals during non-operation periods (¶[0083], [0097]; FIG. 10-12));
storing of refresh parameters (e.g., Mode register set 190/290 includes refresh time register 192 and fail bit mode register 194; refresh clock controller 273a-c stores and adjusts refresh parameters (FIG. 5, 10-12; ¶[0052]-[0056], [0090]-[0097]);
combining temperature code with other parameters to generate refresh period (e.g., Refresh clock controller 273c calculates optimal refresh time tRC_opt with reference to total refresh time, acceptable fail bits, and current temperature information C_temp (¶[0096]-[0097]; FIG. 12));
performing a second self-refresh operation for the memory area within a second refresh period based on the temperature code and the second error flag (e.g. [0049]-[0050] – performing a plurality of refresh operation).
D1 fails to explicitly teach:
generating a second error flag during the first self-refresh operation;
in response to determining that the second error flag is not generated, storing an addition code corresponding to the first self-refresh operation, and performing a second self-refresh operation with a longer refresh period generated by combining the temperature code with the stored addition code; and
Incrementing the stored addition code by a predetermined code value relative to an addition code used to generate the first refresh period
However, D2 teaches:
Generating error flags during self-refresh operation: ECC engine 20 detects whether errors occur in monitoring bits; monitoring is performed periodically during self-refresh mode (FIG. 1-2, ¶[0021], [0026]-[0027]);
Generating a second error flag during the first self-refresh operation: Refresh cycle determining circuit 40 supplies timing signal TS to monitoring address storage unit whenever predetermined time Δt passes; monitoring bits are read and checked for errors during self-refresh (¶[0021], [0027]; FIG. 4 steps S140, S150, FIG. 5 steps S240, S250);
In response to determining that an error flag is not generated, performing a subsequent self-refresh with longer period: If monitoring bit (bit(0)) is normal (no error), the self-refresh cycle tREF increases (FIG. 4 step S154; ¶[0026]);
Storing/adjusting refresh cycle values incrementally: The self-refresh cycle is repeatedly adjusted based on error detection; the process inherently involves storing the current cycle value and modifying it—when all monitoring bits are normal, the cycle increases (FIG. 4-5; ¶[0026]-[0029]);
Incremental increase when no error detected: The method teaches increasing the refresh cycle when the most leaky monitoring bit is normal (no error), which inherently involves incrementing from a prior value (¶[0026], claim 9);
Cycle-to-cycle modification based on prior result: After setting an initial cycle, the device waits predetermined time Δt, rechecks errors, and adjusts again—this is iterative feedback based on prior operation (FIG. 5 steps S160, S240-S256; ¶[0027]).
Thus, D1 provides the framework of temperature-compensated, error-aware refresh control with register-based parameter storage, and D2 provides the specific feedback mechanism of checking for errors during refresh and incrementally lengthening the refresh period when no errors occur. Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to combine D2’s error-based adaptive refresh control with D1’s temperature- and scenario-based self-refresh mechanism in order to create a system that uses temperature and error information (D1) to set an initial refresh period, then applies D2's adaptive feedback to incrementally lengthen that period when error-free operation is confirmed.
Claim 9: D1 teaches a semiconductor memory device, comprising: a cell array including a plurality of memory cells (e.g. item 210, fig. 9); an error correction circuit (e.g. item 265) configured to generate an error flag during a self-refresh operation of the cell array; a temperature sensor (e.g. item 295) configured to detect an operation temperature of the semiconductor memory device and generate a temperature code; a dynamic refresh period generator (e.g. item 270) configured to generate a refresh period for the self-refresh operation by combining the temperature code and the error flag; and a refresh controller performing a self-refresh operation for the cell array according to the refresh period (e.g. [0079]). D1 fails to explicitly teach:
generating a second error flag during the first self-refresh operation;
in response to determining that the second error flag is not generated, storing an addition code corresponding to the first self-refresh operation, and performing a second self-refresh operation with a longer refresh period generated by combining the temperature code with the stored addition code; and
Incrementing the stored addition code by a predetermined code value relative to an addition code used to generate the first refresh period
However, D2 teaches:
Generating error flags during self-refresh operation: ECC engine 20 detects whether errors occur in monitoring bits; monitoring is performed periodically during self-refresh mode (FIG. 1-2, ¶[0021], [0026]-[0027]);
Generating a second error flag during the first self-refresh operation: Refresh cycle determining circuit 40 supplies timing signal TS to monitoring address storage unit whenever predetermined time Δt passes; monitoring bits are read and checked for errors during self-refresh (¶[0021], [0027]; FIG. 4 steps S140, S150, FIG. 5 steps S240, S250);
In response to determining that an error flag is not generated, performing a subsequent self-refresh with longer period: If monitoring bit (bit(0)) is normal (no error), the self-refresh cycle tREF increases (FIG. 4 step S154; ¶[0026]);
Storing/adjusting refresh cycle values incrementally: The self-refresh cycle is repeatedly adjusted based on error detection; the process inherently involves storing the current cycle value and modifying it—when all monitoring bits are normal, the cycle increases (FIG. 4-5; ¶[0026]-[0029]);
Incremental increase when no error detected: The method teaches increasing the refresh cycle when the most leaky monitoring bit is normal (no error), which inherently involves incrementing from a prior value (¶[0026], claim 9);
Cycle-to-cycle modification based on prior result: After setting an initial cycle, the device waits predetermined time Δt, rechecks errors, and adjusts again—this is iterative feedback based on prior operation (FIG. 5 steps S160, S240-S256; ¶[0027]).
Thus, D1 provides the framework of temperature-compensated, error-aware refresh control with register-based parameter storage, and D2 provides the specific feedback mechanism of checking for errors during refresh and incrementally lengthening the refresh period when no errors occur. Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to combine D2’s error-based adaptive refresh control with D1’s temperature- and scenario-based self-refresh mechanism in order to create a system that uses temperature and error information (D1) to set an initial refresh period, then applies D2's adaptive feedback to incrementally lengthen that period when error-free operation is confirmed.
As per claim 18, the claimed features are rejected similarly to claim 1 above. D1 also teaches outputting the number of fail bits (e.g. [0090]), which implies a counter counting the fail bits. Furthermore, D1 teaches performing a plurality of refresh operations (e.g. [0050]).
Claim 2: D1 and D2 implicitly teach the method of claim 1, further comprising: generating a first combination code by adding the temperature code and the first error flag (e.g. D1 teaches combining multiple parameters, including temperature data and error information, to generated the refresh period- See item 270, fig. 9- [0082]) that the memory temperature and the error flag are combine; and determining the first refresh period from the first combination code (e.g. [0082]- D1).
As per claim 10, the claimed features are rejected similarly to claim 2 above.
Claim 3: D1 and D2 implicitly teach the method of claim 2, wherein when the first error flag does not occur, the first combination code is generated by adding a specific code value to the temperature code (e.g. D1 teaches, in [0059], that “in the case where fail bits should not be generated,…the host 10 may write “00” in the fail bit mode register to set tREF to 32 ms.”).
Claim 4: D1 and D2 implicitly teach the method of claim 3, further comprising: generating a second combination code by adding the temperature code and the second error flag; and determining the second refresh period from the second combination code (e.g. D1 teaches, in [0059], that “the host may write “01” in the fail bit register 174 to set the refresh period tREF 10 128ms”).
Claim 5: D1 and D2 implicitly teach the method of claim 4, but fail to teach that when the first error flag and the second error flag do not occur, the second combination code is generated by adding twice the specific code value to the temperature code. However, D2 teaches increasing the refresh period when data errors are not detected (e.g. [0026]). However, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention, to adjust the refresh period to a value greater (e.g. twice) than the first increment value. Such a modification would have been within the general knowledge of an artisan in the art, before the effective filing date of the invention, because it would have involved adjusting the increment valued until an workable value is obtained.
Claim 6: D1 and D2 implicitly teach the method of claim 4, wherein when the first error flag does not occur and the second error flag does occur, the second combination code is generated by adding the specific code value to the temperature code (e.g. D2 teaches adjusting the refresh period of a memory device based on error detection, [0026])).
Claim 7: D1 and D2 implicitly teach the method of claim 1, wherein the first error flag or the second error flag indicates detection of a correctable error from data refreshed in the memory area (e.g. [0090]- D1) .
Claim 8: D1 and D2 implicitly teach the method of claim 1, wherein the first error flag or the second error flag includes a case where an uncorrectable error is detected from data refreshed in the memory area (e.g. [0090]- D1).
Claim 11: D1 and D2 teach the device of claim 10, but fail to teach that the code adder comprises: a code converter generating an addition code corresponding to the error flag; and a plurality of full adders configured to generate the combination code by adding the temperature code and the addition code. However, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention, to use any known computing technique in the teaching of D1 and D2 to add or combine the error flag and the temperature information, since such a modification would have involved applying a known technique to a known device (method, or product) ready for improvement to yield predictable results.
Claim 12: D1 and D2 implicitly teach the device of claim 11, wherein the code converter generates the addition code greater than '1' when the error flag does not occur during the first self-refresh operation (e.g. D2 teaches increasing refresh period when no data errors occur).
Claim 13: D1 and D2 implicitly teach the device of claim 11, wherein the code converter generates the addition code corresponding to '0' when the error flag is generated during the first self-refresh operation (e.g. D2 teaches decreasing refresh period when data errors occur).
Claim 14: D1 and D2 implicitly teach the device of claim 11, but fail to teach that the code converter includes a register for storing a generation history of the addition code. However, both D1 and D2 teaches adjusting the refresh period by a certain value. Therefore, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention, to use any known computing technique in the teaching of D1 and D2 to keep track of the increment value by storing it in a register, since such a modification would have involved been within the general knowledge of an artisan in the art.
Claim 15: D1 and D2 implicitly teach the device of claim 10, wherein the code adder comprises: a register counter counting (e.g. item 194, fig. 11- D1) the number of occurrences of the error flag (e.g. D1 teaches the number of errors or error count – [0080]) and a code converter generating an addition code corresponding to the number of occurrences of the error flag (e.g. the number of fail bits, nFB – [0089]-[0090]- D1) but fail to teach a plurality of full adders configured to generate the combination code by adding the temperature code and the addition code. However, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention, to use any known computing technique in the teaching of D1 and D2 to add or combine the error flag and the temperature information, since such a modification would have involved applying a known technique to a known device (method, or product) ready for improvement to yield predictable results.
Claim 16: D1 and D2 teach the device of claim 9, wherein the dynamic refresh period generator generates a refresh period of a third self-refresh operation executed prior to the first self-refresh operation in the second self-refresh operation when the error flag occurs during the first refresh period. D1 teaches in figure 6B, a first refresh where fail bits are not generated and having a refresh period set to 32mns, and a second refresh succeeding the first refresh with a period refresh set to 128ms (e.g. [0059]). Thus, the second refresh taught by D1 has a refresh period longer than the first refresh. And D2 teaches the technique of adjusting the refresh period of a memory device based on error detection, wherein the refresh period is prolonged when no error is detected and shortened when an error is detected (e.g. [0026]).
Claim 17: D1 and D2 teach the device of claim 9, wherein the dynamic refresh period generator sequentially performs a plurality of self-refresh operations and gradually increases the refresh period until the error flag occurs. D1 teaches in figure 6B, a first refresh where fail bits are not generated and having a refresh period set to 32mns, and a second refresh succeeding the first refresh with a period refresh set to 128ms (e.g. [0059]). Thus, the second refresh taught by D1 has a refresh period longer than the first refresh. And D2 teaches the technique of adjusting the refresh period of a memory device based on error detection, wherein the refresh period is prolonged when no error is detected and shortened when an error is detected (e.g. [0026]).
Claim 19: D1 and D2 implicitly teach the method of claim 18, wherein when the number of occurrences of the second error flag is '1' or more, the second refresh period is shorter than the first refresh period. D1 teaches in figure 6B, a first refresh where fail bits are not generated and having a refresh period set to 32mns, and a second refresh succeeding the first refresh with a period refresh set to 128ms (e.g. [0059]). Thus, the second refresh taught by D1 has a refresh period longer than the first refresh. And D2 teaches the technique of adjusting the refresh period of a memory device based on error detection, wherein the refresh period is prolonged when no error is detected and shortened when an error is detected (e.g. [0026]).
Claim 20: D1 and D2 implicitly teach the method of claim 18, wherein when the number of occurrences of the second error flag is greater than '1', the second refresh period increases in inverse proportion to the number of occurrences of the second error flag compared to the first refresh period. D1 teaches in figure 6B, a first refresh where fail bits are not generated and having a refresh period set to 32mns, and a second refresh succeeding the first refresh with a period refresh set to 128ms (e.g. [0059]). Thus, the second refresh taught by D1 has a refresh period longer than the first refresh. And D2 teaches the technique of adjusting the refresh period of a memory device based on error detection, wherein the refresh period is prolonged when no error is detected and shortened when an error is detected (e.g. [0026]).
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/GUERRIER MERANT/Primary Examiner, Art Unit 2111
3/09/2026