DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Invention I in the reply filed on 04/13/2026 is acknowledged.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1-8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Duesman et al. (U.S. Publication No. 2020/0212032 A1; hereinafter Duesman) in view of Nakayama (U.S. Patent No. 5,535,084)
With respect to claim 1, Duesman discloses a semiconductor device comprising: a first input/output (I/O) interface cell region having a plurality of first electrostatic discharge (ESD) devices [ESD], a first driver [DRV] and a first through silicon via (TSV) disposed therein and having first wiring patterns and first via patterns for electrically connecting the plurality of first ESD devices, the first driver and the first TSV (see Figure 7); and a second I/O interface cell region having a plurality of second ESD devices [ESD], a second driver [DRV] and a second TSV disposed therein and having second wiring patterns and second via patterns for electrically connecting the second driver, the second TSV and a subset of the plurality of second ESD devices, wherein the second ESD devices other than the subset are electrically separated from the second driver and the second TSV, wherein the plurality of first ESD diodes and the plurality of second ESD devices, the first driver and the second driver, and the first TSV and the second TSV have a same structure, and are disposed in a same relative position in the first I/O interface cell region and the second I/O interface cell region (see Figure 7). Duesman fails to disclose wherein the ESD protection devices are diodes. In the same field of endeavor, Nakayama discloses wherein the ESD protection devices are diodes (see Nakayama Column 9, lines 26-31). Implementation of diodes for ESD protection allows for high speed reaction to absorb large energy surges (see Nakayama Column 9, lines 26-31). Therefore, it would have been obvious to one of ordinary skill in the art at the time of invention that the combination of references would arrive at the claimed invention.
With respect to claim 2, the combination of Duesman and Nakayama discloses wherein the first wiring patterns and the second wiring patterns are disposed in a same relative position in the first I/O interface cell region and the second I/O interface cell region, and the second via patterns include via patterns for connecting the subset of the second ESD diodes to at least one of the second wiring patterns, and are electrically separated from the second ESD diodes other than the subset (see Duesman Figure 7).
With respect to claim 3, the combination of Duesman and Nakayama discloses wherein the first via patterns and the second via patterns are disposed in a same relative position in the first I/O interface cell region and the second I/O interface cell region, and the second wiring patterns include at least one wiring pattern configured to electrically connect the subset of the second ESD diodes, the second driver and the second TSV, and electrically separated from via patterns connected to the second ESD diodes other than the subset (see Duesman Figure 7).
With respect to claim 4, the combination of Duesman and Nakayama discloses wherein each of the plurality of first ESD diodes has a same ESD performance (see Duesman Figure 7, ¶[0027] and Nakayama Column 9, lines 26-31)
With respect to claim 5, the combination of Duesman and Nakayama discloses wherein each of the plurality of first ESD diodes has a same number of unit diodes (see Duesman Figure 7, ¶[0027] and Nakayama Column 9, lines 26-31)
With respect to claim 6, the combination of Duesman and Nakayama discloses wherein the first driver, the plurality of first ESD diodes, and the first TSV are disposed in a first direction parallel with a plane on which the first I/O interface cell region is defined (see Duesman Figure 7)
With respect to claim 7, the combination of Duesman and Nakayama discloses wherein the plurality of first ESD diodes and the first TSV are arranged in a first direction parallel with a plane on which the first I/O interface cell region is defined, and the first driver is disposed adjacent to the first TSV in a second direction parallel with the plane and intersecting the first direction (see Duesman Figure 7 ¶[0029])
With respect to claim 8, the combination of Duesman and Nakayama discloses wherein the plurality of first ESD diodes are spaced apart from the first TSV by a first distance, and the first driver is spaced apart from the first TSV by a second distance longer than the first distance (see Duesman Figure 7).
Claim(s) 9-12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Duesman in view of Nakayama as applied to claim 1 above, and further in view of
Karp et al. (U.S. Publication No. 2012/0002392 A1; hereinafter Karp With respect to claim 9, the combination of Duesman and Nakayama fails to explicitly disclose wherein each of the first driver and the second driver includes a first inverter and a plurality of second inverters connected in parallel to an output terminal of the first inverter, wherein the first I/O interface cell region further comprises: a third driver including a plurality of third inverters connected in parallel to each other, and the second I/O interface cell region further comprises: a fourth driver including a plurality of fourth inverters connected in parallel to each other, but does disclose multiple drivers see ¶[0026]). In the same field of endeavor, Karp teaches wherein each of the first driver and the second driver includes a first inverter and a plurality of second inverters connected in parallel to an output terminal of the first inverter, wherein the first I/O interface cell region further comprises: a third driver including a plurality of third inverters connected in parallel to each other, and the second I/O interface cell region (see ¶[0048] and ¶[0058]). Implementing an inverter within the I/O device of the combination of Duesman and Nakayama as taught by Karp allows for a circuit with a forward bias impedance able to be controlled by the ESD device (see Karp ¶[0011]). Therefore, it would have been obvious to one of ordinary skill in the art at the time of invention that the combination of references would arrive at the claimed invention
With respect to claim 10, the combination of Duesman, Nakayama, and Karp discloses wherein a number of the plurality of second inverters, a number of the plurality of third inverters, and a number of the plurality of fourth inverters are identical to each other (see Karp ¶[0047-0048]).
With respect to claim 11, the combination of Duesman, Nakayama, and Karp discloses wherein the first wiring patterns and the first via patterns include wiring patterns and via patterns for connecting the plurality of third inverters in parallel to the plurality of second inverters (see Karp ¶[0047-0048]).
With respect to claim 12, the combination of Duesman, Nakayama, and Karp discloses wherein the second wiring patterns and the second via patterns are electrically separated from the plurality of fourth inverters (see Karp ¶[0047-0048]).
Claim(s) 17-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Duesman in view of Nakayama and Karp. With respect to claim 17, Duesman discloses an input/output (I/O) interface cell comprising: a first driver [DRV]; a second driver [DRV]; a first electrostatic discharge (ESD) device [ESD] including a plurality of first unit diodes, each including a first diode connected between a first power source and an output terminal of the first driver and a second diode connected between a second power source and the output terminal of the first driver; a second ESD device including a plurality of second unit device; and a through silicon via (TSV) electrically connected to the output terminal of the first driver, and the plurality of second unit diodes are selectively connected in parallel with the plurality of first unit diodes depending on the wiring pattern (See Figure 7) Duesman fails to disclose wherein the ESD protection devices are diodes or wherein the first driver including a first inverter and a plurality of second inverters connected in parallel to an output terminal of the first inverter wherein the plurality of third inverters of the second driver are selectively connected in parallel to the plurality of second inverters depending on a wiring pattern. In the same field of endeavor, Nakayama discloses wherein the ESD protection devices are diodes (see Nakayama Column 9, lines 26-31). Furthermore, Karp teaches wherein the first driver including a first inverter and a plurality of second inverters connected in parallel to an output terminal of the first inverter wherein the plurality of third inverters of the second driver are selectively connected in parallel to the plurality of second inverters depending on a wiring pattern (see Karp ¶[0047-0048]). Implementation of diodes for ESD protection allows for high speed reaction to absorb large energy surges (see Nakayama Column 9, lines 26-31). Implementing an inverter within the I/O device of the combination of Duesman and Nakayama as taught by Karp allows for a circuit with a forward bias impedance able to be controlled by the ESD device (see Karp ¶[0011]).Therefore, it would have been obvious to one of ordinary skill in the art at the time of invention that the combination of references would arrive at the claimed invention.
With respect to claim 18, the combination of Duesman, Nakayama and Karp discloses wherein a number of the plurality of second inverters is identical to a number of the plurality of third inverters (see Karp ¶[0047-0048]).
With respect to claim 19, the combination of Duesman, Nakayama and Karp discloses wherein a number of the plurality of first unit diodes is identical to a number of the plurality of second unit diodes (See Duesman Figure 7 and Karp ¶[0047-0048]).
With respect to claim 20, the combination of Duesman, Nakayama and Karp discloses wherein the I/O interface cell comprises: a third driver including a plurality of fourth inverters selectively connected in parallel to the plurality of second inverters depending on the wiring pattern; and a third ESD diode including a plurality of third unit diodes selectively connected in parallel with the plurality of second unit diodes depending on the wiring pattern (see Karp ¶[0047-0048]).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JONATHAN HAN whose telephone number is (571)270-7546. The examiner can normally be reached 9.00-5.00PM PST.
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/JONATHAN HAN/Primary Examiner, Art Unit 2818
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