DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group I, including claims 1-19, in the reply filed on 12/29/2025 is acknowledged.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-4, 7-8 and 13-19 are rejected under 35 U.S.C. 103 as being unpatentable over Sun et al. (PG Pub. No. US 2022/0149005 A1) in view of Oliver et al. (PG Pub. No. US 2018/0013052 A1).
Regarding claim 1, Sun teaches a modular computing structure (fig. 2: 200), comprising:
a plurality of chips (¶ 0029, 0168: 204, 206);
a plurality of attachment structures (¶ 0030: 201, 202), wherein at least some of the attachment structures have a different thickness (¶ 0037, fig. 2: 201 and 202 have different heights);
at least one chip of the plurality of chips is bonded to a first attachment structure of the plurality of attachment structures having a first thickness (fig. 2: 204 bonded to 202); and
a second attachment structure of the plurality of attachment structures adjacent the first attachment structures (fig. 2: 201 adjacent to 202), wherein:
the second attachment structure has a second thickness different from the first thickness of the first attachment structure (¶ 0037: 201 has different height than 202); and
the at least one of the plurality of chips bonded to the first attachment structures extends beyond a footprint of the first attachment structure so the at least one of the chips overlaps at least the second attachment structures (fig. 2: 204 extends beyond boundary of 202 to overlap 201).
Sun does not teach the chips comprise qubit chips.
Oliver teaches a modular quantum computing structure (fig. 14) including a plurality of qubit chips (¶ 0232: 256a, 256b), wherein at least one of the plurality of qubit chips is bonded to a first attachment structure (fig. 14: 256a bonded to TSV substrate 241a).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to configure the chips of Sun as qubit chips, as a means to provide a superconducting integrated circuit (Oliver, ¶ 0010).
Regarding claim 2, Sun in view of Oliver teaches the modular quantum computing structure according to claim 1, wherein the plurality of attachment structures are selected from the group consisting of a laminate, a PCB, an interposer, and another qubit chip (Sun, ¶¶ 201, 202 comprise a substrate and/or a bridge, meeting the broadest reasonable interpretation of an interposer).
Regarding claim 3, Sun in view of Oliver teaches the modular quantum computing structure according to claim 1, wherein the plurality of attachment structures comprise a first interposer and a second interposer of a plurality of interposers (Sun, 202 and 201), and
wherein at least another one of the plurality of qubit chips is bonded to the second interposer (Sun, fig. 2: 206, as modified to include a qubit chip of Oliver, bonded to second 202), and wherein the qubit chips bonded to the first interposer and the qubit chips bonded to the second interposer are bump bonded (Sun, ¶¶ 0033-0034: 204 bonded to first 202 by bumps 242a, 206 bonded to 201 by bumps 232a).
Regarding claim 4, Sun in view of Oliver teaches the modular quantum computing structure according to claim 3, comprising first and second interposers with different thicknesses (Sun, fig. 2: 202, 201 have different heights).
Sun in view of Oliver as applied to claim 3 above does not teach wherein the first interposer is thinner than the second interposer.
However, Oliver teaches a modular quantum computing structure (fig. 14 among others) including a qubit chip disposed on first and second interposers (fig. 14: 256a disposed on 241a and 280),
wherein the first interposer is thinner than the second interposer (fig. 14: 241a thinner than 280).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to configure the interposers of Sun in view of Oliver with the thicknesses of Oliver, as a means to provide interchip qubit coupling as well as create a superconducting signal path between the chips (Oliver, ¶ 0237).
Furthermore, such a modification would have involved a mere change in the size (thickness) of a component (interposer). A change in size is generally recognized as being within the level of ordinary skill in the art In re Rose, 105 USPQ 237 (CCPA 1955).
Regarding claim 7, Sun in view of Oliver teaches the modular quantum computing structure according to claim 3, further comprising one or more standoffs (Sun, ¶ 0035: pillars 230a) arranged on a surface of the second interposer (Sun, fig. 2: 230a arranged on surface of 201) and configured to maintain a uniform gap between the qubit chips extending from the first interposer that overlaps the second interposer (fig. 2: 230a configured with height suitable to maintain a uniform gap between 204/206 overlapping 201).
Regarding claim 8, Sun in view of Oliver teaches the modular quantum computing structure according to claim 3, wherein the plurality of interposers further includes solder-bonded surface mounted connectors (Sun, ¶ 0035: 202, 201 include solder-bonded surface mounted connectors 242, 262, and/or 232).
Regarding claim 13, Sun teaches an electronic structure (fig. 2: 200) comprising:
a plurality of interposers (¶ 0030: bridge die 201 and substrate(s) 202), each interposer having a different thicknesses (¶ 0037 & fig. 2: 201, 202 have different heights);
a plurality of chips (¶ 0030: 204, 206) attached to the plurality of interposers (fig. 2: 204, 206 attached to 201 and/or 202);
one or more of the plurality of chips bonded on a first interposer having a first thickness (fig. 2: 204 bonded on first 202 with a first height) and extending beyond a footprint of the first interposer (fig. 2: 204 extends beyond footprint of first 202), wherein at least one of the chips bonded on the first interposer overlaps a second interposer of the plurality of interposers (fig. 2: 204 overlaps 201); and
another one or more of the plurality of the chips bonded on the second interposer having a second thickness (fig. 2: 206 bonded on 201), wherein at least one of the chips bonded on the second interposer overlaps a third interposer having a third thickness (fig. 2: 206 bonded on second 202 have a third height equal to the first height).
Sun does not teach the chips comprise qubit chips.
Oliver teaches a modular quantum computing structure (fig. 14) including a plurality of qubit chips (¶ 0232: 256a, 256b), wherein a first qubit chip is bonded to a first interposer (fig. 14: 256a bonded to TSV substrate 241a), and a second qubit chip is bonded to a second interposer (fig. 14: 256b bonded to TSV substrate 241b).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to configure the chips of Sun as qubit chips, as a means to provide a superconducting integrated circuit (Oliver, ¶ 0010).
Regarding claim 14, Sun in view of Oliver teaches the electronic structure according to claim 13, comprising the second thickness of the second interposer (Sun, 201) and the third thickness of the third interposer (Sun, second 202).
Sun in view of Oliver does not teach wherein the second thickness of the second interposer and the third thickness of the third interposer are the same.
However, Sun does teach embodiments wherein the substrate comprises more than one cavity (¶ 0031), and therefore teaches embodiments with more than two interposers 202 and/or more than one interposer 201.
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to adjust the third interposer thickness of Sun in view of Oliver, as a means to provide electrical connection to chips with various heights/thicknesses, as a means to improve electrical performance and/or provide a more compact form factor (Sun, ¶ 0037).
Furthermore, such a modification would have involved a mere change in the size (height/thickness) of a component (second or third interposer). A change in size is generally recognized as being within the level of ordinary skill in the art In re Rose, 105 USPQ 237 (CCPA 1955).
In addition, it would have been an obvious matter of design choice bounded by well- known manufacturing constraints and ascertainable by routine experimentation and optimization to choose these particular dimensions because applicant has not disclosed that the dimensions are for a particular unobvious purpose, produce an unexpected result, or are otherwise critical, and it appears prima facie that the process would possess utility using another dimension. Indeed, it has been held that mere dimensional limitations are prima facie obvious absent a disclosure that the limitations are for a particular unobvious purpose, produce an unexpected result, or are otherwise critical. See, for example, In re Rose, 220 F.2d 459, 105 USPQ 237 (CCPA 1955); In re Rinehart, 531 F.2d 1048, 189 USPQ 143 (CCPA 1976); Gardner v. TEC Systems, Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984); In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966).
Regarding claim 15, Sun in view of Oliver teaches the electronic structure according to claim 14, further comprising metal standoffs (Sun, ¶¶ 0038, 0047: pillars 230a, 260) arranged on the second interposer having the second thickness (Sun, fig. 2: 230a arranged on 201) and on the third interposer having the third thickness (Sun, fig. 2: 260 arranged on second 202), wherein the first interposer having the first thickness is aligned between the second interposer and the third interposer on a backing plate (Sun, ¶ 0029 & fig. 2: at least a portion of first 202 laterally arranged between edges of 201 and second 202).
Regarding claim 16, Sun in view of Oliver teaches the structure according to claim 13, comprising first, second, and third interposers (Sun, 202, 201).
Sun in view of Oliver does not teach wherein:
the first interposer having the first thickness is thinner than the second interposer having the second thickness; and
the second interposer having the second thickness is thinner than the third interposer having the third thickness.
However, Sun does teach embodiments wherein the substrate comprises more than one cavity (¶ 0031), and therefore teaches embodiments with more than two interposers 202 and/or more than one interposer 201.
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to adjust the first, second and/or third interposer thickness of Sun in view of Oliver, as a means to provide electrical connection to chips with various heights/thicknesses, as a means to improve electrical performance and/or provide a more compact form factor (Sun, ¶ 0037).
Furthermore, such a modification would have involved a mere change in the size (height/thickness) of a component (first, second or third interposer). A change in size is generally recognized as being within the level of ordinary skill in the art In re Rose, 105 USPQ 237 (CCPA 1955).
In addition, it would have been an obvious matter of design choice bounded by well- known manufacturing constraints and ascertainable by routine experimentation and optimization to choose these particular dimensions because applicant has not disclosed that the dimensions are for a particular unobvious purpose, produce an unexpected result, or are otherwise critical, and it appears prima facie that the process would possess utility using another dimension. Indeed, it has been held that mere dimensional limitations are prima facie obvious absent a disclosure that the limitations are for a particular unobvious purpose, produce an unexpected result, or are otherwise critical. See, for example, In re Rose, 220 F.2d 459, 105 USPQ 237 (CCPA 1955); In re Rinehart, 531 F.2d 1048, 189 USPQ 143 (CCPA 1976); Gardner v. TEC Systems, Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984); In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966).
Regarding claim 17, Sun in view of Oliver teaches the electronic structure according to claim 13, further comprising a backing plate (Sun, ¶ 0029: PCB), wherein the first interposer, the second interposer, and the third interposer are arranged on a same surface of the backing plate in a stepped arrangement based on a relative thickness of the interposers (¶ 0029 & fig. 2: 201, 202 at least indirectly arranged on surface of PCB based on thickness of 201/202).
Regarding claim 18, Sun in view of Oliver teaches the electronic structure according to claim 13, wherein each of the plurality of qubit chips is bump bonded to the interposers (¶ 0033 & fig. 2: 204 bonded to first 202 with bumps 242, 206 bonded to second 202 with bumps 262).
Regarding claim 19, Sun in view of Oliver teaches the electronic structure according to claim 13, further comprising:
a plurality of multi-layer wirings (MLW) arranged within the interposers (Sun, ¶ 0042 & fig. 2: multilevel horizontal wiring arranged in 201 and/or 202); and
a plurality of thru-substrate vias (TSVs) arranged within the interposers (Sun, fig. 2: plurality of vertical interconnects arranged in 201 and/or 202),
wherein the MLW layers are connected to the TSVs and the TSVs to connected to the qubit chips (Sun, fig. 2: wirings in 201/202 electrically connected to vertical interconnects, and vertical interconnects electrically connected to 204/206, as modified to include qubit chips of Oliver).
Claims 9-11 are rejected under 35 U.S.C. 103 as being unpatentable over Sun in view of Oliver as applied to claim 3 above, and further in view of Yohannes et al. (PG Pub. No. US 2022/0237495 A1).
Regarding claim 9, Sun in view of Oliver teaches the modular quantum computing structure according to claim 3, comprising a plurality of quantum computing structures (Oliver, fig. 14: 256a, 256b, 280).
Sun in view of Oliver does not teach a plurality of modules formed by a plurality of quantum computing structures aligned to form an air-gapped connection between a qubit chip of the plurality of qubit chips of one module and an interposer of an adjacent module of the plurality of modules.
Yohannes teaches a modular quantum computing structure comprising a plurality of quantum computing structures (¶ 0023: 102, 104) aligned to form an air-gapped connection between a qubit chip of the plurality of qubit chips of one module and an interposer of an adjacent module of the plurality of modules (¶¶ 0023, 0054 & figs. 5AQ-5B: 102 and 104 capacitively and/or inductively coupled, and therefore includes an inter-module air gap).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to configure the modular quantum computing structure of Sun in view of Oliver with the air-gapped connection of Yohannes, as a means to provide simplicity of fabrication, design flexibility and/or increased density of integration (Yohannes, ¶ 0056).
Regarding claim 10, Sun in view of Oliver and Yohannes teaches the modular quantum computing structure according to claim 9, further comprising a bus across the air-gap connection between the qubit chip of the one module and the interposer of the adjacent module of the plurality of modules, wherein one or more qubit chips on one or more adjacent modules of the plurality of modules are capacitively coupled by the bus (Yohannes, ¶ 0054: 102, 104 capacitively coupled).
Regarding claim 11, Sun in view of Oliver and Yohannes teaches the modular quantum computing structure according to claim 9, further comprising a bus across the air-gap connection between the qubit chip of one module and the interposer of the adjacent module of the plurality of modules, wherein the plurality of qubit chips bonded on one or more adjacent modules of the plurality of modules are inductively coupled by the bus (Yohannes, ¶ 0054: 102, 104 inductively coupled).
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Sun in view of Oliver and Yohannes as applied to claim 9 above, and further in view of Sinclair et al. (PG Pub. No. US 2023/0400788 A1).
Regarding claim 12, Sun in view of Oliver and Yohannes teaches the modular quantum computing structure according to claim 9, further comprising a backing plate (Sun, ¶ 0029: PCB), wherein the plurality of modules is attached to the backing plate (Sun, ¶ 0029: each module is at least electrically attached to PCB).
Sun in view of Oliver and Yohannes does not teach wherein the backing plate includes an alignment ridge.
Sinclair teaches a computing structure including modules (fig. 1) disposed on a substrate (fig. 2), the substrate including alignment features (¶ 0094).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to configure the backing plate Sun in view of Oliver and Yohannes to include an alignment ridge, as a means to assist in positioning of the modules and ensure proper air gap formation.
Allowable Subject Matter
Claims 5-6 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: The prior art fails to teach or clearly suggest the limitations stating:
“a backing plate; and
a third interposer having qubit chips bonded thereon, wherein:
the third interposer has a thickness that is the same as the second interposer;
the first interposer is arranged on the backing plate between the second interposer and the third interposer; and
the at least one of qubit chips bonded to the first interposer extends beyond the footprint of the first interposer to overlap both the second interposer and the third interposer” as recited in claim 5.
Claim 6 depends on claim 5 and is allowable for the same reasons.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Kikuchi et al. (US 2023/0162080 A1) teaches a quantum computing device (¶ 0068: 1) including a qubit chip (10) extending beyond a footprint of an interposer (fig. 1A: 10 extends beyond footprint of interposer 30).
Elsherbini et al. (US 2019/0042964 A1) teaches a quantum computing device (¶ 0022: 100) including qubit chips bump bonded to an interposer (fig. 3).
Abraham et al. (US 2023/0359917 A1) teaches a quantum computing device including QC chip modules arranged in a tiled formation to form an air-gapped connection between a qubit chip of a first QC chip module and an interposer chip of a neighboring QC chip module (claim 9).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BRIAN TURNER whose telephone number is (571)270-5411. The examiner can normally be reached M-F 8am-5pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eva Montalvo can be reached at 571-270-3829. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/BRIAN TURNER/ Examiner, Art Unit 2818