DETAILED ACTION
Specification
1. The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Rejections - 35 USC § 102
2. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
3. Claim(s) 1 – 3, 5, 10 – 15, 17, 20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Song et al. (8957413).
With regard to claim 1, Song et al. disclose a display panel (for example, see fig. 5) comprising:
a cathode unit area (referred to as “A1” by examiner’s annotation shown in fig. 5 below; wherein the unit area A1, including a cathode layer OE2 based on an anode layer OE1 for forming a light emitting device OLED, functioning as the cathode unit area A1; for example, column 6, lines 32 - 36),
a spacing area (referred to as “A2” by examiner’s annotation shown in fig. 5 below) disposed outside the cathode unit area (A1) and adjacent to the cathode unit area (A1), wherein the cathode unit area is provided with at least one pixel area (a pixel area including OLED and transistor T1);
wherein the display panel further comprises:
a thin film transistor layer (referred to as “B1” by examiner’s annotation shown in fig. 5 below; wherein the layer B1, including layers having a thin film transistor T1 and an auxiliary electrode SE1, functioning as a thin film transistor layer) wherein comprising an auxiliary cathode wiring (a first auxiliary electrode SE1, is electrically connected to the cathode electrode OE2, functioning as an auxiliary cathode wiring);
a first conductive layer (layer portions SE2, ED, SE3 functioning as a first conductive layer) disposed on the thin film transistor layer (B1), wherein the first conductive layer (SE2, ED, SE3) comprises a connection electrode (SE2) disposed surrounding the cathode unit area (A1) and connected to the auxiliary cathode wiring (SE1), and a side wall (ED) of the connection electrode (SE2) is in a concave shape (an undercut opening OP, as annotated in fig. 5 below, inherently having a hollow shape that an electrode region SE3 is formed and functioning as a concave shape, under the sidewall ED of the connection electrode SE2) form an undercut opening (referred to as “OP” by examiner’s annotation shown in fig. 5 below) disposed surrounding the cathode unit area (A1);
a light-emitting functional layer (OL) disposed on a side (a top side) of the first conductive layer (SE2, ED, SE3) away from the thin film transistor layer (B1) and partitioned at the undercut opening (OP); and
a cathode layer (CE2) disposed on a side (a top side) of the light-emitting functional layer (OL) away from the thin film transistor layer (B1) and partitioned at the undercut opening (OP);
wherein the cathode layer (CE2) comprises a first cathode (referred to as “CE2A” by examiner’s annotation shown in fig. 5) disposed within the cathode unit area (A1), and the connection electrode (SE2) is disposed surrounding the first cathode (CE2A) and connected to the first cathode (CE2A).
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With regard to claim 2, Song et al. disclose the display panel further comprises a pixel definition layer (referred to as “PDL” by examiner’s annotation shown in fig. 5 below) disposed between the first conductive layer (SE2, ED, SE3) and the light-emitting functional layer (OL), and the pixel definition layer (PDL) comprises a first opening (referred to as “OP1” by examiner’s annotation shown in fig. 5 below) disposed within the pixel area (the pixel area including OLED and transistor T1) and a second opening (referred to as “OP2” by examiner’s annotation shown in fig. 5 below) disposed corresponding to the connection electrode (SE2); and wherein the light-emitting functional layer (OL) comprises a light-emitting part (referred to as “OL1” by examiner’s annotation shown in fig. 5 below) disposed in the first opening (OP1), at least a part (SE3) of the connection electrode (SE2) is disposed in the second opening (OP2), and the undercut opening (OP) is communicated with the second opening (OP2); the first cathode (OE2A) covers the light-emitting part (OL1) within the cathode unit area (A1), extends into the second opening (OP2), and is connected to the connection electrode (SE2).
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With regard to claim 3, Song et al. disclose the connection electrode (SE2) is disposed at least within the spacing area (A2), the cathode layer (OE2) further comprises a second cathode (referred to as “OE2A2” by examiner’s annotation shown in fig. 5 below) disposed within the spacing area (A2), and the second cathode (OE2A2) and the first cathode (OE2A) are spaced apart.
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With regard to claim 5, Song et al. disclose an orthographic projection of the connection electrode (SE2) on the thin film transistor layer (B1) partially overlaps with an orthographic projection of the second opening (OP2) on the thin film transistor layer (B1); the undercut opening (OP) is disposed on a side of the connection electrode (SE2) close to the first cathode (OE2A), and the first cathode (OE2A) and the second cathode (OE2A2) are spaced at the undercut opening (OP).
With regard to claim 10, Song et al. disclose the first conductive layer (layer portions SE2, ED, SE3, or SE2, ED, SE3, OE1 functioning as a first conductive layer) further comprises an anode (OE1) disposed within the pixel area (the pixel area including OLED and transistor T1), and the light-emitting part (OL1) is disposed in the first opening (OP1) and on a side of the anode (OE1) away from the thin film transistor layer (B1).
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With regard to claim 11, Song et al. disclose the connection electrode (SE2) comprises a first sub-layer (referred to as “SE2C1” by examiner’s annotation shown in fig. 5 below) and a second sub-layer (referred to as “SE2C2” by examiner’s annotation shown in fig. 5 below) disposed in stack, the second sub-layer (SE2C2) is disposed between the first sub-layer (SE2C1) and the thin film transistor layer (B1), and a side wall of the second sub-layer (SE2C2) is in a concave shape (a via hole, forming in the interlayer, inherently having a concave shape) relative to a side wall of the first sub-layer (SE2C1) to form the undercut opening (OP) at a side wall of the connection electrode (SE2).
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With regard to claim 12, Song et al. disclose the connection electrode (SE2) comprises a first sub-layer (referred to as “SE2C1” by examiner’s annotation shown in fig. 5 below), a second sub-layer (referred to as “SE2C2” by examiner’s annotation shown in fig. 5 below) and a third sub-layer (referred to as “SE2C3” by examiner’s annotation shown in fig. 5 below) disposed in stack, wherein the second sub-layer (SE2C2) is disposed between the first sub-layer (SE2C1) and the third sub-layer (SE2C3), the third sub-layer (SE2C3) is disposed between the second sub-layer (SE2C2) and the thin film transistor layer (B1), and both of a side wall of the second sub-layer (SE2C2) and a side wall of the third sub-layer (SE2C3) are in a concave shape (a via hole, forming in the interlayer, inherently having a concave shape) relative to a side wall of the first sub-layer (SE2C1) to form the undercut opening (OP).
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With regard to claim 13, Song et al. disclose a display apparatus (for example, see fig. 5) comprising a display panel, wherein the display panel comprising:
a cathode unit area (referred to as “A1” by examiner’s annotation shown in fig. 5 below; wherein the unit area A1, including a cathode layer OE2 based on an anode layer OE1 for forming a light emitting device OLED, functioning as the cathode unit area A1; for example, column 6, lines 32 - 36),
a spacing area (referred to as “A2” by examiner’s annotation shown in fig. 5 below) disposed outside the cathode unit area (A1) and adjacent to the cathode unit area (A1), wherein the cathode unit area is provided with at least one pixel area (a pixel area including OLED and transistor T1);
wherein the display panel further comprises:
a thin film transistor layer (referred to as “B1” by examiner’s annotation shown in fig. 5 below; wherein the layer B1, including layers having a thin film transistor T1 and an auxiliary electrode SE1, functioning as a thin film transistor layer) wherein comprising an auxiliary cathode wiring (a first auxiliary electrode SE1, is electrically connected to the cathode electrode OE2, functioning as an auxiliary cathode wiring);
a first conductive layer (layer portions SE2, ED, SE3 functioning as a first conductive layer) disposed on the thin film transistor layer (B1), wherein the first conductive layer (SE2, ED, SE3) comprises a connection electrode (SE2) disposed surrounding the cathode unit area (A1) and connected to the auxiliary cathode wiring (SE1), and a side wall (ED) of the connection electrode (SE2) is in a concave shape (an undercut opening OP, as annotated in fig. 5 below, inherently having a hollow shape that an electrode region SE3 is formed and functioning as a concave shape, under the sidewall ED of the connection electrode SE2) form an undercut opening (referred to as “OP” by examiner’s annotation shown in fig. 5 below) disposed surrounding the cathode unit area (A1);
a light-emitting functional layer (OL) disposed on a side (a top side) of the first conductive layer (SE2, ED, SE3) away from the thin film transistor layer (B1) and partitioned at the undercut opening (OP); and
a cathode layer (CE2) disposed on a side (a top side) of the light-emitting functional layer (OL) away from the thin film transistor layer (B1) and partitioned at the undercut opening (OP);
wherein the cathode layer (CE2) comprises a first cathode (referred to as “CE2A” by examiner’s annotation shown in fig. 5) disposed within the cathode unit area (A1), and the connection electrode (SE2) is disposed surrounding the first cathode (CE2A) and connected to the first cathode (CE2A).
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With regard to claim 14, Song et al. disclose the display panel further comprises a pixel definition layer (referred to as “PDL” by examiner’s annotation shown in fig. 5 below) disposed between the first conductive layer (SE2, ED, SE3) and the light-emitting functional layer (OL), and the pixel definition layer (PDL) comprises a first opening (referred to as “OP1” by examiner’s annotation shown in fig. 5 below) disposed within the pixel area (the pixel area including OLED and transistor T1) and a second opening (referred to as “OP2” by examiner’s annotation shown in fig. 5 below) disposed corresponding to the connection electrode (SE2); and wherein the light-emitting functional layer (OL) comprises a light-emitting part (referred to as “OL1” by examiner’s annotation shown in fig. 5 below) disposed in the first opening (OP1), at least a part (SE3) of the connection electrode (SE2) is disposed in the second opening (OP2), and the undercut opening (OP) is communicated with the second opening (OP2); the first cathode (OE2A) covers the light-emitting part (OL1) within the cathode unit area (A1), extends into the second opening (OP2), and is connected to the connection electrode (SE2).
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With regard to claim 15, Song et al. disclose the connection electrode (SE2) is disposed at least within the spacing area (A2), the cathode layer (OE2) further comprises a second cathode (referred to as “OE2A2” by examiner’s annotation shown in fig. 5 below) disposed within the spacing area (A2), and the second cathode (OE2A2) and the first cathode (OE2A) are spaced apart.
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With regard to claim 17, Song et al. disclose an orthographic projection of the connection electrode (SE2) on the thin film transistor layer (B1) partially overlaps with an orthographic projection of the second opening (OP2) on the thin film transistor layer (B1); the undercut opening (OP) is disposed on a side of the connection electrode (SE2) close to the first cathode (OE2A), and the first cathode (OE2A) and the second cathode (OE2A2) are spaced at the undercut opening (OP).
With regard to claim 20, Song et al. disclose the connection electrode (SE2) comprises a first sub-layer (referred to as “SE2C1” by examiner’s annotation shown in fig. 5 below) and a second sub-layer (referred to as “SE2C2” by examiner’s annotation shown in fig. 5 below) disposed in stack, the second sub-layer (SE2C2) is disposed between the first sub-layer (SE2C1) and the thin film transistor layer (B1), and a side wall of the second sub-layer (SE2C2) is in a concave shape (a via hole, forming in the interlayer, inherently having a concave shape) relative to a side wall of the first sub-layer (SE2C1) to form the undercut opening (OP) at a side wall of the connection electrode (SE2).
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Allowable Subject Matter
4. Claims 4, 16 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claims 4, 16 are allowable over the prior art of record, because none of these references disclose or can be combined to yield the claimed invention such as the undercut opening comprises a first undercut opening disposed on a side of the connection electrode close to the first cathode and a second undercut opening disposed on a side away from the first cathode; the cathode layer further comprises a third cathode disposed on a side of the connection electrode away from the thin film transistor layer and at least within the spacing area; and wherein the first cathode and the third cathode are spaced apart at the first undercut opening, and the second cathode and the third cathode are spaced apart at the second undercut opening as recited in claims 4, 16.
5. Claims 6 – 9, 18, 19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claims 6 – 9, 18, 19 are allowable over the prior art of record, because none of these references disclose or can be combined to yield the claimed invention such as a plurality of cathode unit areas, and the first conductive layer comprises a plurality of connection electrodes disposed surrounding the plurality of cathode unit areas; the cathode layer comprises a plurality of first cathodes disposed within the plurality of cathode unit areas, and the second cathode is disposed between two adjacent cathode unit areas as recited in claims 6, 18.
Conclusion
6. Any inquiry concerning this communication or earlier communications from the examiner should be directed to TAN N TRAN whose telephone number is (571) 272 - 1923. The examiner can normally be reached on 8:30-5:00PM.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Davienne Monbleau can be reached on (571) 272-1945. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/TAN N TRAN/
Primary Examiner, Art Unit 2812