DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-20 have been fully considered but are moot because the arguments are directed to newly added limitations which haven’t been rejected in the previous action, please refer to new ground of rejection for details.
Claim Rejections - 35 USC § 112
3. The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
4.Claims 1-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 1, reciting “first part” and “second part” multiple times, in lines 3-7 and 13, however it’s unclear whether they are referring to a circuitry or a signal; further reciting “processed for respective bandwidth parts of the received signal” in line 8, however it’s unclear description, the bandwidth parts appear to be the bandwidths of the first and second parts of the received signal, if so, it should be clearly recited; further reciting “overlapping bandwidth” in line 9 being vague, according to present figure 6(iii) it appears the frequency bands are overlapping, the term “bandwidth” refers to the width of a band but not frequency of the band in the spectrum, and “overlapping” may also be in time domain of concurrent receptions.
Same arguments applied to claims 13, 18 and 19.
Claims 2-12, 14-17 and 20 are rejected for depend from claim 1 or 13.
Claim Rejections - 35 USC § 103
5. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
6. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
7. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
8. Claim(s) 1, 3, 5-6, 11, 13-15 and 18-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over YU (US 20190200270 A1) in view of Tomioka (US 20060256884 A1).
For claim 1. YU discloses (Abstract, figure 3B, [0045]-[0046]) An apparatus comprising: a first reception path comprising a first low noise amplifier (RX mode, LNA 333-2); a first feedback path comprising a second low noise amplifier (TX feedback mode, LNA 333-1); first downstream receiver circuitry (figure 3B, at least components 335-337); a switching arrangement (figure 3B, switch 354-2) configured to, in a first state, couple the first reception path to the first downstream receiver circuitry (RX mode) and configured to, in a second state, couple the first feedback path to the first downstream receiver circuitry (TX feedback mode); and a controller ([0045], [0084], control circuitry 240) configured to place the switching arrangement in the first state during the reception time slot (RX mode) and in the second state during a transmission time slot (TX feedback mode).
YU fails to mention wherein (i) the apparatus is configured to split the first reception path into at least a first part and a second part, (ii) the first part comprises first frequency shift circuitry configured to introduce a first frequency shift to a received signal in the first part, (iii) the second part comprises second frequency shift circuitry configured to introduce a second frequency shift to the received signal in the second part, (iv) the first part of the received signal and the second part of the received signal are separately processed for respective bandwidth parts of the received signal, and (v) the respective bandwidth parts comprise an overlapping bandwidth for irregular bandwidths or carrier aggregation; second downstream receiver circuitry, wherein the apparatus is configured to couple the second downstream receiver circuitry, during a reception time slot, to the second part of the first reception path.
In the same field of endeavor, Tomioka discloses a radio frequency receiver configured to split the first reception path into at least a first part and a second part (figure 2, overlapping first and second receiving signals of first and second receiving systems), (ii) the first part comprises first frequency shift circuitry configured to introduce a first frequency shift to a received signal in the first part (figure 2 [0035] mixer 7-1; or figure 3 [0041] first unit 18), (iii) the second part comprises second frequency shift circuitry configured to introduce a second frequency shift to the received signal in the second part ([0035] mixer 7-2; or [0041] third/fourth unit 18), (iv) the first part of the received signal and the second part of the received signal are separately processed for respective bandwidth parts of the received signal (figures 2-3), and (v) the respective bandwidth parts comprise an overlapping bandwidth for irregular bandwidths (figures 1, 10 and 12; [0011], [0033]) or carrier aggregation; second downstream receiver circuitry (figure 2 A/D 5-2; or figure 3 second/third demodulator 15), wherein the apparatus is configured to couple the second downstream receiver circuitry, during a reception time slot, to the second part of the first reception path.
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the selection techniques taught by Tomioka into the art of YU as to improve data throughput in multiple receivers system.
For claim 3. YU in combination with Tomioka substantially teaches the apparatus as claimed in claim 1, YU discloses configured to couple the first downstream receiver circuitry, during the transmission time slot, to the first feedback path (figure 3B, [0045]-[0046]).
Tomioka discloses wherein the apparatus is: configured to couple the first downstream receiver circuitry, during a reception time slot, to a first part of the first reception path; configured to couple the second downstream receiver circuitry, during the reception time slot, to a second part of the first reception path (figures 1-3, [0035], [0041]).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the selection techniques taught by Tomioka into the art of YU modified by Tomioka as to improve data throughput in multiple receivers system.
For claim 5. YU in combination with Tomioka substantially teaches an apparatus as claimed in claim 1, YU discloses wherein the switch arrangement is configured to have: a state that couples the first reception path but not the first feedback path to the downstream receiver circuitry; and a state that couples the first feedback path but not the first reception path to the downstream receiver circuitry (figure 3B, [0045]-[0046]).
For claim 6. YU in combination with Tomioka substantially teaches an apparatus as claimed in claim 5, YU discloses (figure 3B, [0045]-[0046]) wherein the switching arrangement comprises: a first switching circuitry (switch 354-2) configured to have a first switching state that enables coupling of the first reception path to the first downstream receiver circuitry and a second switching state that disables coupling of the first reception path to the first downstream receiver circuitry; a second switching circuitry (switch 354-1) configured to have a first switching state that enables coupling of the first feedback path to the first downstream receiver circuitry and a second switching state that disables coupling of the first feedback path to the first downstream receiver circuitry, wherein a switching state that couples the first reception path but not the first feedback path to the first downstream receiver circuitry comprises a first switching state of the first switching circuitry and a second switching state of the second switching circuitry (selecting LNA 333-2); and a switching state that couples the first feedback path but not the first reception path to the first downstream receiver circuitry comprises a second switching state of the first switching circuitry and a first switching state of the second switching circuitry (selecting LNA 333-1).
For claim 11. YU in combination with Tomioka substantially teaches an apparatus as claimed in claim 1, YU discloses wherein the controller is configured to determine a state of the switching arrangement, during a reception time slot, in dependence upon any one or more of: network configuration as regards non-contiguous intra-band carrier aggregation; network configured irregular bandwidth; availability of downstream receiver circuitry; or interference, if any, in frequencies adjacent the received first bandwidth ([0029]-[0030] availability of downstream receiver circuitry in RX time slot for RX mode, [0063]).
For claim 13. YU discloses (Abstract, figure 3B, [0045]-[0046]) A method comprising: during a transmission time slot, couple a first feedback path (LNA 333-1) to a first downstream receiver circuitry (TX feedback mode); and during a reception time slot, couple the first reception path (LNA 333-2) to the first downstream receiver circuitry (RX mode).
YU fails to mention split a first reception path into at least a first part and a second part, wherein the first part comprises first frequency shift circuitry configured to introduce a first frequency shift to a received signal in the first part and the second part comprises second frequency shift circuitry configured to introduce a second frequency shift to the received signal in the second part; process the first part and the second part separately for respective bandwidth parts of the received signal, wherein the respective bandwidth parts comprise an overlapping bandwidth for irregular bandwidths or carrier aggregation; during the reception time slot, couple a second downstream receiver circuitry to the second part of the first reception path.
In the same field of endeavor, Tomioka discloses split a first reception path into at least a first part and a second part (figure 2, overlapping first and second signals of first and second receiving systems), wherein the first part comprises first frequency shift circuitry (figure 2 [0035] mixer 7-1; or figure 3 [0041] first unit 18) configured to introduce a first frequency shift to a received signal in the first part and the second part comprises second frequency shift circuitry ([0035] mixer 7-2; or [0041] third/fourth unit 18) configured to introduce a second frequency shift to the received signal in the second part; process the first part and the second part separately for respective bandwidth parts of the received signal (figures 2-3), wherein the respective bandwidth parts comprise an overlapping bandwidth for irregular bandwidths (figures 1, 10 and 12; [0011], [0033]) or carrier aggregation; during the reception time slot, couple a second downstream receiver circuitry (figure 2 A/D 5-2; or figure 3 second/third demodulator 15) to the second part of the first reception path.
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the selection techniques taught by Tomioka into the art of YU as to improve data throughput in multiple receivers system.
For claim 14. YU in combination with Tomioka substantially teaches a method as claimed in claim 13, YU discloses further comprising: detecting that a timing corresponds to the transmission time slot, and in response to the detecting coupling the first feedback path to the first downstream receiver circuitry ([0056]-[0058]).
For claim 15. YU in combination with Tomioka substantially teaches a method as claimed in claim 13, YU discloses further comprising: detecting that a timing corresponds to the reception time slot, and in response to the detection coupling the first reception path to the first downstream receiver circuitry ([0056]-[0058]).
For claim 18. YU discloses (Abstract, figure 3B, [0045]-[0046]) An apparatus comprising: at least one processor; and at least one memory storing instructions that, when executed by the at least one processor, cause the apparatus at least to: during a transmission time slot (TX feedback mode), couple a first feedback path (LNA 333-1) to a first downstream receiver circuitry; and during a reception time slot (RX mode), couple the first reception path (LNA 333-2) to the first downstream receiver circuitry.
YU fails to mention split a first reception path into at least a first part and a second part, wherein the first part comprises first frequency shift circuitry configured to introduce a first frequency shift to a received signal in the first part and the second part comprises second frequency shift circuitry configured to introduce a second frequency shift to the received signal in the second part; process the first part and the second part separately for respective bandwidth parts of the received signal, wherein the respective bandwidth parts comprises an overlapping bandwidth for irregular bandwidths or carrier aggregation; during the reception time slot, couple a second downstream receiver circuitry to the second part of the first reception path.
In the same field of endeavor, Tomioka discloses split a first reception path into at least a first part and a second part (figure 2, overlapping first and second signals of first and second receiving systems), wherein the first part comprises first frequency shift circuitry (figure 2 [0035] mixer 7-1; or figure 3 [0041] first unit 18) configured to introduce a first frequency shift to a received signal in the first part and the second part comprises second frequency shift circuitry ([0035] mixer 7-2; or [0041] third/fourth unit 18) configured to introduce a second frequency shift to the received signal in the second part; process the first part and the second part separately for respective bandwidth parts of the received signal (figures 2-3), wherein the respective bandwidth parts comprises an overlapping bandwidth for irregular bandwidths (figures 1, 10 and 12; [0011], [0033]) or carrier aggregation; during the reception time slot, couple a second downstream receiver circuitry (figure 2 A/D 5-2; or figure 3 second/third demodulator 15) to the second part of the first reception path.
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the selection techniques taught by Tomioka into the art of YU as to improve data throughput in multiple receivers system.
For claim 19. YU discloses (Abstract, figure 3B, [0045]-[0046]) A non-transitory computer readable medium comprising program instructions stored thereon for performing at least the following: (switch 354-2) during a transmission time slot, couple a first feedback path (LNA 333-1) to a first downstream receiver circuitry (TX feedback mode); and during a reception time slot, couple the first reception path (LNA 333-2) to the first downstream receiver circuitry (RX mode).
YU fails to mention split a first reception path into at least a first part and a second part, wherein the first part comprises first frequency shift circuitry configured to introduce a first frequency shift to a received signal in the first part and the second part comprises second frequency shift circuitry configured to introduce a second frequency shift to the received signal in the second part; process the first part and the second part separately for respective bandwidth parts of the received signal, wherein the respective bandwidth parts comprises an overlapping bandwidth for irregular bandwidths or carrier aggregation; during the reception time slot, couple a second downstream receiver circuitry to the second part of the first reception path.
In the same field of endeavor, Tomioka discloses split a first reception path into at least a first part and a second part (figure 2, overlapping first and second signals of first and second receiving systems), wherein the first part comprises first frequency shift circuitry (figure 2 [0035] mixer 7-1; or figure 3 [0041] first unit 18) configured to introduce a first frequency shift to a received signal in the first part and the second part comprises second frequency shift circuitry ([0035] mixer 7-2; or [0041] third/fourth unit 18) configured to introduce a second frequency shift to the received signal in the second part; process the first part and the second part separately for respective bandwidth parts of the received signal (figures 2-3), wherein the respective bandwidth parts comprises an overlapping bandwidth for irregular bandwidths (figures 1, 10 and 12; [0011], [0033]) or carrier aggregation; during the reception time slot, couple a second downstream receiver circuitry (figure 2 A/D 5-2; or figure 3 second/third demodulator 15) to the second part of the first reception path.
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the selection techniques taught by Tomioka into the art of YU as to improve data throughput in multiple receivers system.
For claim 20. YU in combination with Tomioka substantially teaches the apparatus of claim 1, YU discloses (Abstract) User equipment comprising the apparatus of claim 1.
9. Claim(s) 2 is/are rejected under 35 U.S.C. 103 as being unpatentable over YU as modified by Tomioka above, in view of Megretski (US 20210152201 A1).
For claim 2. YU in combination with Tomioka substantially teaches the apparatus as claimed in claim 1, YU discloses wherein the first feedback path is configured to receive transmission signals on a transmission path, the apparatus comprising means for processing received transmission signals received via the first feedback path and first downstream receiver circuitry, during the transmission time slot (figure 3B, [0045]-[0046]).
But fails to mention to control envelope tracking and digital pre-distortion (DPD) of transmission signals transmitted via the transmission path.
This teaching is disclosed by Megretski (figure 1, [0075], [0085]-[0086], [0130], feedback samples y for controlling envelope tracking e_A and DPD coefficients).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the selection techniques taught by Megretski into the art of YU modified by Tomioka as to improve power amplifier efficiency.
10. Claim(s) 4, 9-10 and 16-17 is/are rejected under 35 U.S.C. 103 as being unpatentable over YU modified by Tomioka above, in view of Behzad (US 20080137770 A1).
For claim 4. YU in combination with Tomioka substantially teaches the apparatus as claimed in claim 1, but fails to disclose comprising multiple reception paths including the first reception path and a second reception path; wherein the switch arrangement is configured to couple the first downstream receiver circuitry, during a reception time slot, to the any one of the multiple reception paths and configured to couple the first downstream receiver circuitry, during a transmission time slot, to the first feedback path.
Behzad (FIG. 2A, [0062]) discloses a transceiver comprising multiple reception paths including the first reception path (226a) and a second reception path (226b); wherein the switch arrangement (234) is configured to couple the first downstream receiver circuitry (228, 230, 232), during a reception time slot, to the any one of the multiple reception paths and configured to couple the first downstream receiver circuitry, during a transmission time slot, to the first feedback path (220).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the selection techniques taught by Behzad into the art of YU modified by Tomioka as to improve application including IQ signals.
For claim 9. YU in combination with Tomioka substantially teaches the apparatus as claimed in claim 1, but fails to disclose configured to separately control frequency offsets applied to the first reception path and the first feedback path before processing via the first downstream receiver circuitry.
This teaching is disclosed by Behzad (FIG. 2A, [0062], mixers 220 and 226 for frequency offsets).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the selection techniques taught by Behzad into the art of YU modified by Tomioka as to include IQ down conversions as a further embodiment.
For claim 10. YU in combination with Tomioka substantially teaches the apparatus as claimed in claim 1, but fails to disclose wherein the controller is configured to place the switching arrangement in the first state to support reception of a first bandwidth, wherein the switching arrangement is configured in the first state to enable processing of the received first bandwidth as a plurality of overlapping bandwidths wherein one of the plurality of overlapping bandwidths is processed via the first downstream receiver circuitry and another one of the plurality of overlapping bandwidths is processed via a second downstream receiver circuitry, and/or wherein the controller is configured to place the switching arrangement in the first state to support carrier aggregation, wherein the switching arrangement is configured in the first state to enable processing of a first component carrier by the first downstream receiver circuitry and processing of a second component carrier by a second downstream receiver circuitry.
Behzad (FIG. 2A and 2B, [0062]) discloses a transceiver comprising a controller is configured to place the switching arrangement (switch 236) in the first state to support reception of a first bandwidth (received I and Q signals), wherein the switching arrangement is configured in the first state to enable processing of the received first bandwidth as a plurality of overlapping bandwidths (I and Q bandwidths) wherein one of the plurality of overlapping bandwidths (I bandwidth) is processed via the first downstream receiver circuitry and another one of the plurality of overlapping bandwidths (Q bandwidth) is processed via a second downstream receiver circuitry (separate I and Q downstream receivers), and/or wherein the controller is configured to place the switching arrangement in the first state to support carrier aggregation, wherein the switching arrangement is configured in the first state to enable processing of a first component carrier by the first downstream receiver circuitry and processing of a second component carrier by a second downstream receiver circuitry.
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the selection techniques taught by Behzad into the art of YU modified by Tomioka as to include IQ down conversions as a further embodiment.
For claim 16. YU in combination with Tomioka substantially teaches the method as claimed in claim 13, but fails to disclose further comprising: wherein the first downstream receiver circuitry comprises analogue baseband circuitry that includes analogue filtration circuitry.
This teaching is disclosed by Behzad (FIG. 2A, [0062]: LPF 230a).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the selection techniques taught by Behzad into the art of YU modified by Tomioka as to improve signal quality.
For claim 17. YU in combination with Tomioka and Behzad substantially teaches the method as claimed in claim 16, YU discloses further comprising: wherein the analogue baseband circuitry is re-used for different applications (figure 3B, components 335-337 for RX mode and TX feedback mode).
11. Claim(s) 7-8 is/are rejected under 35 U.S.C. 103 as being unpatentable over YU as modified by Tomioka above, in view of GAYNOR (US 20230231550 A1).
For claim 7. YU in combination with Tomioka substantially teaches the apparatus as claimed in claim 1, YU discloses wherein the switching arrangement is configured to enable coupling of the first reception path to first downstream receiver circuitry by selectively coupling a first upstream node (node in switch 354-1) coupled to the first reception path and a first downstream node (node in switch 354-2) coupled to the first downstream receiver circuitry and disable coupling of the first reception path to the first downstream receiver circuitry by selectively decoupling the first upstream node and the first downstream node (figure 3B, [0045]-[0046]).
But fails to disclose terminating the first upstream node to ground and the first downstream node to ground.
This teaching is disclosed by GAYNOR (figures 1 and 2, [0036] switch OFF state M12 shunting to ground of both nodes P and T1, [0040] switch ON state M12 very high e.g. open circuit).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the selection techniques taught by GAYNOR into the art of YU modified by Tomioka as to improve switching process/isolation.
For claim 8. YU in combination with Tomioka substantially teaches the apparatus as claimed in claim 1, YU discloses wherein the switching arrangement is configured to enable coupling of the first feedback path to first downstream receiver circuitry by selectively coupling an upstream node (node in switch 354-1) coupled to the first feedback path and a downstream node (node in switch 354-2) coupled to the first downstream receiver circuitry and disable coupling of the first feedback path to the first downstream receiver circuitry by selectively decoupling the upstream node and the downstream node (figure 3B, [0045]-[0046]).
But fails to disclose terminating the upstream node to ground and the downstream node to ground.
This teaching is disclosed by GAYNOR (figures 1 and 2, [0036] switch OFF state M12 shunting to ground of both nodes P and T1, [0040] switch ON state M12 very high e.g. open circuit).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the selection techniques taught by GAYNOR into the art of YU modified by Tomioka as to improve switching process/isolation.
12. Claim(s) 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over YU as modified by Tomioka above, in view of Liu (US 8971350 B1).
For claim 12. YU in combination with Tomioka substantially teaches the apparatus as claimed in claim 1, but fails to disclose wherein the controller is configured to: update capability information provided to a network in dependence upon availability of downstream receiver circuitry.
This teaching is disclosed by Liu (figures 1 and 6, column 2 lines 45-61, claim 17, updating the first receiver availability).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the selection techniques taught by Liu into the art of YU modified by Tomioka as to improve communication management or synchronization.
13. Claims 18 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Behzad (US 20080137770 A1) in view of Nilsson (US 20160072656 A1).
For claim 18, Behzad discloses (FIG. 2A and 2B, [0062]) An apparatus comprising: at least one processor; and at least one memory storing instructions that, when executed by the at least one processor, cause the apparatus at least to: split a first reception path into at least a first part and a second part (figure 2A, first part mixer 226a, second part mixer 226b), wherein the first part comprises first frequency shift circuitry (mixer 226a) configured to introduce a first frequency shift to a received signal in the first part and the second part comprises second frequency shift circuitry (mixer 226b) configured to introduce a second frequency shift to the received signal in the second part; process the first part and the second part separately for respective bandwidth parts of the received signal (I and Q signals), wherein the respective bandwidth parts comprises an overlapping bandwidth (I and Q signals); during a transmission time slot, couple a first feedback path (mixer 220a) to a first downstream receiver circuitry (228a, 230a, 232a); during a reception time slot, couple the first reception path (226a) to the first downstream receiver circuitry (228a, 230a, 232a); and during the reception time slot, couple a second downstream receiver circuitry (228b, 230b, 232b) to the second part of the first reception path (226b).
But fails to mention for irregular bandwidths or carrier aggregation.
This teaching is disclosed by Nilsson ([0034], [0037], [0041], overlapping I and Q components for carrier aggregation).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the selection techniques taught by Nilsson into the art of Behzad as to improve data throughput in carrier aggregation system.
For claim 19, since it is program claim of claim 18 and has similar limitation, so it’s rejected under the same basis as claim 18 set forth above.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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Any inquiry concerning this communication or earlier communications from the examiner should be directed to Rui Meng Hu whose telephone number is 571-270-1105, email is ruimeng.hu@uspto.gov. The examiner can normally be reached on Monday - Friday, 8:00 a.m. - 5:00 p.m., EST.
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/Rui Meng Hu/
R.H./rh
March 30, 2026
/JINSONG HU/ Supervisory Patent Examiner, Art Unit 2643
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