DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-3, 5, 7-18 and 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lee (US 2021/0098367).
Regarding claim 1, Lee discloses a semiconductor device comprising:
a substrate (400, fig. 5 and paragraph 0052);
gate electrodes on an upper surface of the substrate (331, fig. 5), the gate electrodes including pads disposed in a stepped shape (331, fig. 5 and paragraphs 0008, 0042, 0059), the gate electrodes being spaced apart from each other in a first direction (331, fig. 5 separated by insulating layer 307), the first direction perpendicular to the upper surface of the substrate, the gate electrodes including a first gate electrode (top 331, fig. 5) and second gate electrodes (331 below top 331, fig. 5), the second gate electrodes below the first gate electrode;
a channel extending in the first direction through the gate electrodes (313, fig. 5 and paragraph 0058);
a first through via passing through and electrically connected to a first pad of the first gate electrode (333, fig. 5 and paragraph 0060), the first through via passing through the second gate electrodes (333, fig. 5 and paragraph 0060), the first through via including a conductive pillar extending in the first direction and a connection portion connected to the conductive pillar (333, fig. 5 and paragraph 0060), the connection portion being in contact with the first pad of the first gate electrode (protrusion portion of 333, fig. 5 and paragraph 0060);
a first separation insulating layer on an upper surface of the connection portion of the first through via (321, fig. 5 and paragraphs 0061, 0073);
a second separation insulating layer on a bottom surface of the connection portion of the first through via (327, fig. 5 and paragraph 0060); and
an insulating pattern between the first through via and sidewalls of the second gate electrodes opposing the first through via (327, fig. 5 and paragraph 0060).
Regarding claim 2, it is inherent that wherein the first separation insulating layer and the second separation insulating layer have rounded sidewalls protruding outward toward the pad, and the pad has a protruding portion conforming to the shape of the rounded sidewalls of the first separation insulating layer and the second separation insulating layer since the semiconductor manufacturing process disclosed produces rounded characteristics in lieu of the 90 degree angles depicted in fig. 5.
Regarding claim 3, Lee further discloses wherein, in a plan view, the first
separation insulating layer and the second separation insulating layer have an annular shape (fig. 16).
Regarding claim 5, Lee further discloses comprising:
a sidewall insulating layer surrounding a sidewall of the first through via (fig. 5 and paragraph 0060), wherein the sidewall insulating layer is connected to the first separation insulating layer and the second separation insulating layer, and
the sidewall insulating layer is connected to the insulating pattern (fig. 5 and paragraph 0060).
Regarding claim 7, Lee further discloses further comprising:
mold insulating layers between the gate electrodes (307, fig. 5 and paragraph 0054); and a cover insulating layer covering the pads on the gate electrodes (323, fig. 5 and paragraph 0061), wherein an upper surface of the first pad and an upper surface of the first separation insulating layer are covered by the cover insulating layer (323, fig. 5 and paragraph 0061).
Regarding claim 8, Lee further discloses wherein the first separation
insulating layer is between the connection portion and the cover insulating layer (323, fig. 5 and paragraph 0061).
Regarding claim 9, Lee further discloses a blocking insulating layer on upper surfaces and sidewalls of the gate electrodes (323, fig. 5 and paragraph 0061), wherein
a first portion of the blocking insulating layer is between the first pad and a sidewall of the first separation insulating layer (fig. 5).
Regarding claim 10, Lee further discloses wherein the first portion of the blocking insulating layer has a bottom surface at a level higher than a bottom surface of the first separation insulating layer (fig. 5), and the connection portion comprises a tuck portion in contact with the first portion of the blocking insulating layer (fig. 5).
Regarding claim 11, Lee further discloses wherein the first portion of the blocking insulating layer (323, fig. 5) is not disposed on at least a portion of a sidewall of the first pad facing the first through via (interior portion around 333, fig. 5),
a second portion of the blocking insulating layer is on a sidewall of the second gate electrodes facing the first through via (323, fig. 5).
Regarding claim 12, Lee further discloses wherein the insulating pattern
comprises a seam therein (327, fig. 5 and paragraph 0060, seam is between 327 and 307).
Regarding claim 13, Lee further discloses a wedge pattern between a sidewall of the insulating pattern and a sidewall of the first through via (top portion of 327 below protrusion, fig. 5 and paragraph 0060).
Regarding claim 14, Lee further discloses a circuit pattern on the substrate (110, fig. 5 and paragraph 0048);
a wiring pattern on the substrate and electrically connected to the circuit pattern (303, fig. 5 and paragraph 0053);
a lower interlayer insulating film on the substrate and covering the circuit pattern and the
wiring pattern (301, fig. 5 and paragraph 0053); and
a common source plate on the lower interlayer insulating film (305, fig. 5 and paragraph 0065), wherein the gate electrodes are on the common source plate (331, fig. 5), and
the first through via penetrates the common source plate and is electrically connected to
the wiring pattern (333 connected to 303, fig. 5).
Regarding claim 15, Lee discloses a semiconductor device comprising:
a cell stack on a substrate, the cell stack including gate electrodes (331, fig. 5 and paragraph 0058) and mold insulating layers (307, fig. 5 and paragraph 0058) alternately disposed in a first direction perpendicular to an upper surface of the substrate, the gate electrodes including step-shaped pads (331, fig. 5 and paragraphs 0008, 0042, 0059), the cell stack further including a cover insulating layer (323, fig. 5 and paragraph 0061) covering the step-shaped pads, the gate electrodes including a first gate electrode (top 331, fig. 5) and second gate electrodes, the second gate electrodes below the first gate electrode (331 below top 311, fig. 5);
a channel passing through the cell stack and extending in the first direction (313, fig. 5 and paragraph 0058);
a first through via (333, fig. 5 and paragraph 0060) passing through the cell stack and extending in the first direction, the first through via being connected to a first pad of the first gate electrode and passing through the second gate electrodes (fig. 5), the first through via including a conductive pillar (333, fig. 5 and paragraph 0060) and a connection portion (protrusion on 333, fig. 5 and paragraph 0060),
the connection portion protruding outward laterally from the conductive pillar (fig.5);
an insulating pattern between the first through via and sidewalls of the second gate electrodes opposing the first through via, the insulating pattern electrically insulating the first through via and the second gate electrodes from each other (327, fig. 5 and paragraph 0060);
a sidewall insulating layer surrounding sidewalls of the conductive pillar of the first through via (327, fig. 5 and paragraph 0060); and
a first separation insulating layer on an upper surface of the connection portion of the first through via (321, fig. 5 and paragraph 0061).
Regarding claim 16, Lee further discloses wherein the first separation insulating layer is between the connection portion and the cover insulating layer, and
the first separation insulating layer is integrally connected to the sidewall insulating layer (fig. 5).
Regarding claim 17, Lee further discloses a blocking insulating layer on upper surfaces of the gate electrodes and sidewalls of the gate electrodes (323, fig. 5 and paragraph 0061),
wherein a first portion of the blocking insulating layer is between the first pad and a sidewall of the first separation insulating layer (fig. 5), and
wherein a second portion of the blocking insulating layer is on sidewalls of the second gate electrode facing the first through via (fig. 5).
Regarding claim 18, Lee further discloses wherein a bottom surface of the first portion of the blocking insulating layer is at a higher level higher than a bottom surface of the first separation insulating layer, and the connection portion comprises a tuck portion in contact with the first portion of the blocking insulating layer (fig. 5).
Regarding claim 20, Lee discloses a semiconductor device comprising:
a substrate (400, fig. 5 and paragraph 0052);
a circuit pattern on the substrate (110, fig. 5 and paragraph 0048);
a wiring pattern on the substrate and electrically connected to the circuit pattern (303, fig. 5 and paragraph 0053);
a lower interlayer insulating film on the substrate, the lower interlayer insulating film covering the circuit pattern and the wiring pattern (301, fig. 5 and paragraph 0053);
a common source plate on the lower interlayer insulating film (305, fig. 5 and paragraph 0065);
gate electrodes on the common source plate, the gate electrodes being spaced apart from each other in a first direction perpendicular to an upper surface of the substrate, the gate electrodes including pads disposed in a stepped shape (331, fig. 5 and paragraphs 0008, 0042, 0059), the gate electrodes including a first gate electrode (top 331, fig. 5) and second gate electrodes, the second gate electrodes below the first gate electrode (331 below top 331, fig. 5);
a channel extending in the first direction through the gate electrodes (313, fig. 5 and paragraph 0058);
a first through via passing through and electrically connected to a first pad of the first gate electrode (333, fig. 5 and paragraph 0060), the first through via passing through the second gate electrodes (333, fig. 5 and paragraph 0060), the first through via including a conductive pillar extending in the first direction and a connection portion connected to the conductive pillar (333, fig. 5 and paragraph 0060), the connection portion being in contact with the first pad of the first gate electrode (protrusion portion of 333, fig. 5 and paragraph 0060);
a sidewall insulating layer surrounding a sidewall of the conductive pillars of the first
through via (fig. 5);
a first separation insulating layer on an upper surface of the connection portion of the first through via (321, fig. 5 and paragraphs 0061, 0073);
a second separation insulating layer on a bottom surface of the connection portion of the first through via (327, fig. 5 and paragraph 0060); and
an insulating pattern between the first through via and sidewalls of the second gate electrodes facing the first through via (327, fig. 5 and paragraph 0060).
a blocking insulating layer on upper surfaces of the gate electrodes and sidewalls of the gate electrodes, the blocking insulating layer including a first portion between the first pad and a sidewall of the first separation insulating layer (323, fig. 5 and paragraph 0061).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 4, 6 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Lee (US 2021/0098367).
Lee discloses the devices of claims 1, 5 and 15, as mentioned above. Lee does not explicitly disclose the relative thicknesses of the layers mentioned in claims 4, 6, and 19, however, such relative thicknesses are deemed to be obvious to one of ordinary skill in the art at the time of filing given normal reasonable experimentation of Lee’s teachings.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. US Patent Application Publications 20210134832 and 20160240476 disclose relevant three dimensional memory structures with stair stepped gate structures.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DOUGLAS M MENZ whose telephone number is (571)272-1877. The examiner can normally be reached Monday-Friday 8:00am-5:00pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jacob Choi can be reached at 469-295-9060. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/DOUGLAS M MENZ/Primary Examiner, Art Unit 2897 3/20/26
/JACOB Y CHOI/Supervisory Patent Examiner, Art Unit 2897