DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
Claims 18-20 have been canceled; Claims 1, 7, 11, and 17 have been amended; and claims 1-17 and 21-23 are currently pending.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 4-5, 8-11, 13, and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Baek et al. (US 2019/0304992 A1, hereinafter “Baek”) in view of Lee et al. (US 2022/0013538 A1, hereinafter “Lee”).
In regards to claim 1, Baek discloses (See, for example, Fig. 2) a semiconductor device comprising:
a circuit area including a peripheral circuit structure (Fig. 2); and
a cell area (CELL + PAD) on the circuit area, wherein the cell area (CELL+PAD) includes:
a cell array area (CELL);
a connection area (PAD);
a gate stacking structure (110, 130) including a plurality of gate electrodes (111-116, 131-136),
wherein the gate stacking structure (110, 130) includes an upper structure (130) on the circuit area and a lower structure (110) between the upper structure (130) and the circuit area;
a plurality of channel structures (CH1) that penetrates the gate stacking structure (110, 130) in the cell array area (CELL); and
a plurality of gate contact portions (contact portion between 170 and gate electrodes) that penetrates the gate stacking structure (110, 130) in the connection area (PAD),
wherein the plurality of gate electrodes (11-116, 131-136) comprises a bottom gate electrode (136) in a bottom portion of the upper structure (130),
wherein a gate contact portion (Ra) among the plurality of gate contact portions is electrically connected to the circuit area and a connection gate electrode of the plurality of gate electrodes and is electrically insulated from remaining gate electrodes of the plurality of gate electrodes by an insulating pattern (120, 140, 161, 162) between the gate contact portion and the remaining gate electrodes,
wherein the bottom gate electrode (136) in the cell array area is adjacent to a channel structure (CH1) among the plurality of channel structures, and
wherein a bottom insulating portion (147, 162) having a structure and/or a material different from the insulating pattern ((141-146)) is in the bottom portion of the upper structure (130) and adjacent to the gate contact portion (Pa).
Baek is silent about wherein a gate contact portion in the connection area is electrically connected to the circuit area and a connection gate electrode of the plurality of gate electrodes and is electrically insulated from remaining gate electrodes of the plurality of gate electrode by an insulating pattern horizontally between the gate contact portion and the remaining gate electrodes.
Lee while disclosing a semiconductor memory device teaches (See, for example, Fig. 4) wherein a gate contact portion (310/320) in the connection area is electrically connected to the circuit area (PS) and a connection gate electrode (See, for example, 260 corresponding to 241) of the plurality of gate electrodes (141-146, 241-246) and is electrically insulated from remaining gate electrodes of the plurality of gate electrode by an insulating pattern (270) horizontally between the gate contact portion (310/320) and the remaining gate electrodes (other than 241).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the invention to modify Baek by Lee because this would help route every gate electrode to the peripheral circuit through a single self-isolated vertical contact rather than through separate stepped contacts and overlying connection wiring, thereby reducing the horizontal area consumed by the connection area and improving the integration density and wiring simplicity of the semiconductor device.
In regards to claim 2, Baek discloses (See, for example, Fig. 2) the bottom gate electrode (136) in the connection area is separated from the gate contact portion (Pa) by the bottom insulating portion (147, 162).
In regards to claim 4, Baek discloses (See, for example, Fig. 2) the bottom gate electrode (136) is in contact with the lower structure (110).
In regards to claim 5, Baek discloses (See, for example, Fig. 2) the bottom insulating portion (147, 162) includes an oxide (See, for example, Pars [0026]-[0027].
In regards to claim 8, Baek discloses (See, for example, Fig. 2) a peripheral width of the bottom insulating portion (147, 162) is greater than a width of the insulating pattern (141-146).
In regards to claim 9, Baek discloses (See, for example, Fig. 2) the bottom insulating portion (147, 162) has a circular shape, an elliptical shape, a polygon shape, or a line shape in a plan view (See, for example, fig. 1).
In regards to claim 10, Baek discloses (See, for example, Fig. 2) the bottom insulating portion (147, 162) at least partially extends around the gate contact portion (Pa, Ra) in a plan view.
In regards to claim 11, Baek discloses (See, for example, Fig. 2) the connection area includes a pad area (PAD) in which the connection gate electrode ((See, for example, 136) is included in the upper structure and the gate contact portion (170) are connected to each other, and wherein the bottom insulating portion (147, 162) is in the pad area (PAD).
In regards to claim 13, Baek discloses (See, for example, Fig. 2) the bottom insulating portion (147, 162) includes a single insulating material, and wherein the insulating pattern (141-146) includes a plurality of insulation layers (See, for example, Par [0026]-[0027]), a step profile on an upper surface or a lower surface of the insulating pattern, a part of a blocking layer (151), or a part of a gate electrode among the plurality of gate electrodes.
In regards to claim 16, Baek discloses (See, for example, Fig. 2) the bottom insulating portion (147, 162) extends around the plurality of gate contact portions (Pa, Ra) in a plan view.
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Baek in view of Park and Lee.
In regards to claim 17, Baek discloses (See, for example, Fig. 2) an electronic system comprising:
wherein the semiconductor device includes
a circuit area including a peripheral circuit structure (Fig. 2); and
a cell area (CELL + PAD) on the circuit area, and wherein the cell area (CELL+PAD) includes:
a cell array area (CELL);
a connection area (PAD);
a gate stacking structure (110, 130) including a plurality of gate electrodes (111-116, 131-136),
wherein the gate structure (110, 130) includes a lower structure (110) and an upper structure (130) on the lower structure (110);
a channel structure (CH1) that penetrates the gate stacking structure (110, 130) in the cell array area, wherein the plurality of gate electrodes includes a bottom gate electrode (136) in a bottom portion of the upper structure (130),
wherein a gate contact portion (Ra) in the connection area is electrically connected to the circuit area and a connection gate electrode of the plurality of gate electrodes and is electrically insulated from remaining gate electrodes of the plurality of gate electrodes by an insulating pattern (120, 140, 161, 162) between the gate contact portion and the remaining gate electrodes,
wherein the bottom gate electrode (136) in the cell array area is adjacent to a channel structure (CH1), and
wherein a bottom insulating portion (147, 162) having a structure and/or a material different from the insulating pattern ((141-146)) is in the bottom portion of the upper structure (130) and adjacent to the gate contact portion (Pa).
Baek is silent about a main substrate;
a semiconductor device on the main substrate; and
a controller electrically connected to the semiconductor device.
Park while disclosing a memory device teaches (See, for example, Figs. 1 and 4) a main substrate (10);
a semiconductor device (CELL + PERI) on the main substrate (10); and
a controller (7, Fig. 1) electrically connected to the semiconductor device (2, Fig. 1).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the invention to modify Baek by Park because this will help prevent the punching defects during the formation of the gate contact holes.
Baek is silent about wherein a gate contact portion in the connection area is electrically connected to the circuit area and a connection gate electrode of the plurality of gate electrodes and is electrically insulated from remaining gate electrodes of the plurality of gate electrode by an insulating pattern horizontally between the gate contact portion and the remaining gate electrodes.
Lee while disclosing a semiconductor memory device teaches (See, for example, Fig. 4) wherein a gate contact portion (310/320) in the connection area is electrically connected to the circuit area (PS) and a connection gate electrode (See, for example, 260 corresponding to 241) of the plurality of gate electrodes (141-146, 241-246) and is electrically insulated from remaining gate electrodes of the plurality of gate electrode by an insulating pattern (270) horizontally between the gate contact portion (310/320) and the remaining gate electrodes (other than 241).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the invention to modify Baek by Lee because this would help route every gate electrode to the peripheral circuit through a single self-isolated vertical contact rather than through separate stepped contacts and overlying connection wiring, thereby reducing the horizontal area consumed by the connection area and improving the integration density and wiring simplicity of the semiconductor device.
Allowable Subject Matter
Claims 3, 6-7, 12, 14 and 15 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim 21 are allowed over prior art of record.
The following is an examiner' s statement of reasons for allowance: The prior art of record neither anticipates nor renders obvious the claimed subject matter
of the instant application as a whole either taken alone or in combination, in particular, prior art of record does not teach The bottom portion of the upper structure includes a first bottom portion adjacent to a channel structure among the plurality of channel structures in the cell array area, the bottom portion of the upper structure includes a second bottom portion adjacent to the gate contact portion in the connection area, and wherein the first bottom portion includes a structure and/or a material different from the second bottom portion.
Claims 22-23 are also allowed as being dependent of the allowed independent base claim.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Response to Arguments
Applicant’s arguments with respect to claims 1 and 17 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Correspondence
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERMIAS T WOLDEGEORGIS whose telephone number is (571)270-5350. The examiner can normally be reached on Monday-Friday 8 am - 5 pm E.S.T..
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Britt Hanley can be reached on 571-270-3042. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ERMIAS T WOLDEGEORGIS/Primary Examiner, Art Unit 2893
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