DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 10/09/2023 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Election/Restrictions
Applicant’s election with traverse of Group I, and Claims 1-16 in the reply filed on 03/30/2026 is acknowledged. The traversal on the grounds that the inventions of Group I and Group II are not independent or distinct and there would be no serious burden on the examiner has been found persuasive. The inventions of Groups I and II share common technical features and no search burden was involved. Hence the restriction has been withdrawn.
Claims 1-20 have been examined.
Drawings
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(4) because reference character “513” has been used to designate both “power pads” and “first main input diode.” Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Objections
Claim 6 is objected to because of the following informalities:
Claim 6 recites “the second sub pad of one of the second memory chips included in the first group and the second main pad of one second memory chip of the second memory chips included in the second group are electrically connected to each other by a third internal interconnection structure.” This should be rewritten as “the second sub pad of one of the second memory chips included in the first group and the second main pad of one of the second memory chips included in the second group are electrically connected to each other by a third internal interconnection structure.”
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1 - 16 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites “a second sub pad electrically connected to the second main pad” It is unclear if the second sub pad is associated with one particular “second memory chip” or if it is associated with any one of the plurality of second memory chips. It is unclear if the second sub pads are provided one per each second memory chip or there is only one second sub pad associated with the plurality of second memory chips. For the purpose of examination, the Examiner interprets the second sub pads are provided one per each one of the second memory chips.
Claim 1 recites “electrically connected to the first sub pad by a first internal interconnection structure”. It is unclear whether the interconnection structure is internal to the second memory chip, or the stacked structure or the semiconductor system. It is unclear if there is one or multiple “first internal interconnection structure”. For the purpose of examiner, the Examiner interprets this as one first internal interconnection structure which is internal to the semiconductor system.
Claim 2 recites “wherein the second sub pad included in the one second memory chip of the one or more second memory chips is electrically connected to the first sub pad by the first internal interconnection structure.” It is unclear if each of the second sub pads connect to the first sub pad or only one of the second sub pads connect to the first sub pad. For the purpose of examination, the Examiner interprets this as only one of the second sub pads connect to the first sub pad.
Claims 2 - 6 recites the “a second internal interconnection structure”; it is unclear if these interconnection structures are distinct from each other or they are the same interconnection structure. For the purpose of examination, the Examiner interprets this as the same interconnection structure.
Claim 6 recites “respective second sub pads of second memory chips included in the first group are electrically connected to each other by a second internal interconnection structure, and respective second sub pads of second memory chips included in the second group are electrically connected to each other by a second internal interconnection structure.” It is unclear if “second internal interconnection structure” refers to the two different second interconnection structures or two different instances of the same “second interconnection structure”.
For the purpose of examination, the Examiner interprets this limitation as “respective second sub pads of second memory chips included in the first group are electrically connected to each other by a second internal interconnection structure, and respective second sub pads of second memory chips included in the second group are electrically connected to each other by another second internal interconnection structure.
Claim 6 recites “the second sub pad of one of the second memory chips included in the first group and the second main pad of one second memory chip of the second memory chips included in the second group are electrically connected to each other by a third internal interconnection structure.” The specification does not define “a third internal interconnection structure”. For the purpose of examination, the Examiner interprets this limitation as an “internal interconnection structure.”
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-5, 7, 11-13 and 15-18 are rejected under 35 U.S.C. 103 as being unpatentable over Sasaki (US20080230888A1; hereinafter Sasaki) in view of Asano et al. (US20110016266A1; hereinafter Asano).
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Sasaki: FIG. 1
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Asano: FIG. 5
Regarding Claim 1, Sasaki discloses a semiconductor system (semiconductor package 100, FIG. 1 reproduced above, [0051]) comprising:
a substrate (mounting board 101), FIG. 1, [0051];
a first memory chip (first memory chip 103a) supported by the substrate (101), FIG. 1, [0051],
wherein the first memory chip (103a) includes a first main pad (113a) structured to be electrically connected to an interconnection structure (first wire 115 and first stitches 109) disposed outside the first memory chip (first stitches 109 are disposed on 101 outside first chip 113a), FIG. 1, [0055], [0058].
Sasaki [0054] discloses pads 113a and 113b are control pads, address pads, or data pads on each chip and functions as a control terminal, an address terminal or data terminal, thus 113a and 113b are interpreted as the first and second main pads respectively. Sasaki discloses pads 121a and 121b as chip select pads and are interpreted as first and second sub pads.
a first sub pad (121a) on first memory chip (103a), FIG. 1, [0054].
and one or more second memory chips (second memory chip 103b) supported by the substrate (101), FIG. 1, [0051],
wherein each of the one or more second memory chips (103b) includes a second main pad (113b) structured to be electrically connected to an interconnection structure (first wire 115 and first stitches 109) disposed outside the first memory chip (109 disposed on 101 outside first chip 113a), (113b are connected to the first stitches 109 through the control pads, address pads, or data pads 113a, FIG. 1, [0064]).
and a second sub pad (121b) on second memory chip (103b), FIG. 1, [0054].
Sasaki does not disclose “and a first sub pad electrically connected to the first main pad; a second sub pad electrically connected to the second main pad, and the second main pad or the second sub pad included in one second memory chip of the one or more second memory chips is electrically connected to the first sub pad by a first internal interconnection structure.”
In a similar art, Asano discloses a semiconductor device [0039].
Asano discloses:
a first sub pad (PD1a) electrically connected to the first main pad (PD1b), FIG. 5 reproduced above, [0040]. Asano discloses pad PD1a is connected to internal circuit K11 via resistor R1a; and pad PD1b is connected to the internal circuit K11 via resistor R1b and electrostatic protection circuit CD1. Therefore, the first sub pad PD1a is electrically connected to first main pad PD1b.
Asano [0040] discloses the pad electrodes PD1b and PD2a to PD4a are connected to an external terminal T21 of the semiconductor package via bonding wires BW1 to BW4 and interpreted as the main pads. The pads PD1a, PD2b, PD3b, PD4b are connected to internal circuity and are not directly wire bonded to the terminal T21 and are interpreted as the sub pads.
a second sub pad (PD2b) electrically connected to the second main pad (PD2a), FIG. 5, [0040]. Asano discloses pad PD2a is connected to internal circuit K12 via resistor R2a; and pad PD2b is connected to the internal circuit K12 via resistor R2b and electrostatic protection circuit CD2. Therefore, the second sub pad PD2b is electrically connected to second main pad PD2a.
and the second main pad (PD2a) or the second sub pad included in one second memory chip (CP12) of the one or more second memory chips is electrically connected to the first sub pad (PD1a) by a first internal interconnection structure (Bonding wires BW1, BW2 and terminal T21), FIG. 5, [0040].
Asano discloses that a system as taught prevents reduced operating frequency and increased power consumption [0041]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify Sasaki’s system in order to prevent reduced operating frequency and increased power consumption as disclosed by Asano [0041].
Regarding Claim 2, The combination of Sasaki and Asano discloses the semiconductor system according to claim 1.
Sasaki does not disclose “wherein the second sub pad included in the one second memory chip of the one or more second memory chips is electrically connected to the first sub pad by the first internal interconnection structure, and is electrically connected to the second sub pad included in another second memory chip of the one or more second memory chips by a second internal interconnection structure.”
Asano discloses: wherein the second sub pad (PD2b) included in the one second memory chip (CP12) of the one or more second memory chips is electrically connected to the first sub pad (PD1a) by the first internal interconnection structure (BW1, BW2 and terminal T21), FIG. 5, [0040].
and is electrically connected to the second sub pad (PD3b) included in another second memory chip (CP13) of the one or more second memory chips by a second internal interconnection structure (BW2, BW3, and T21), FIG. 5, [0040].
Asano discloses that a system as taught prevents reduced operating frequency and increased power consumption [0041]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify Sasaki’s system in order to prevent reduced operating frequency and increased power consumption as disclosed by Asano [0041].
Regarding Claim 3, The combination of Sasaki and Asano discloses the semiconductor system according to claim 1.
Sasaki does not disclose “wherein second sub pads included in two adjacent second memory chips, respectively, of the one or more second memory chips are electrically connected by a second internal interconnection structure.”
Asano discloses: wherein second sub pads (PD2b in chip CP12 and PD3b in chip CP13) included in two adjacent second memory chips (CP12 and CP13), respectively, of the one or more second memory chips are electrically connected by a second internal interconnection structure (BW2, BW3, and T21), FIG. 5, [0040].
Asano discloses that a system as taught prevents reduced operating frequency and increased power consumption [0041]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify Sasaki’s system in order to prevent reduced operating frequency and increased power consumption as disclosed by Asano [0041].
Regarding Claim 4, The combination of Sasaki and Asano discloses the semiconductor system according to claim 1.
Sasaki does not disclose “wherein the second main pad included in the one second memory chip of the one or more second memory chips is electrically connected to the first sub pad by the first internal interconnection structure, and the second sub pad included in the one second memory chip of the one or more second memory chips is electrically connected to the second main pad included in another second memory chip of the one or more second memory chips by a second internal interconnection structure.”
Asano discloses: wherein the second main pad (PD2a) included in the one second memory chip (CP12) of the one or more second memory chips is electrically connected to the first sub pad (PD1a) by the first internal interconnection structure (BW1, BW2, and T21), FIG. 5, [0040].
and the second sub pad (PD2b) included in the one second memory chip (CP12) of the one or more second memory chips is electrically connected to the second main pad (PD3a) included in another second memory chip (CP13) of the one or more second memory chips by a second internal interconnection structure (BW2, BW3, and T21), FIG. 5, [0040].
Asano discloses that a system as taught prevents reduced operating frequency and increased power consumption [0041]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify Sasaki’s system in order to prevent reduced operating frequency and increased power consumption as disclosed by Asano [0041].
Regarding Claim 5, The combination of Sasaki and Asano discloses the semiconductor system according to claim 1.
Sasaki does not disclose “wherein the second main pad included in one second memory chip of two adjacent second memory chips of the one or more second memory chips and the second sub pad included in the other second memory chip of the two adjacent second memory chips are electrically connected by a second internal interconnection structure.”
Asano discloses: wherein the second main pad (PD2a) included in one second memory chip (CP12) of two adjacent second memory chips of the one or more second memory chips and the second sub pad (PD3b) included in the other second memory chip (CP13) of the two adjacent second memory chips are electrically connected by a second internal interconnection structure (BW2, BW3, and T21), FIG. 5, [0040].
Asano discloses that a system as taught prevents reduced operating frequency and increased power consumption [0041]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify Sasaki’s system in order to prevent reduced operating frequency and increased power consumption as disclosed by Asano [0041].
Regarding Claim 7, The combination of Sasaki and Asano discloses the semiconductor system according to claim 1.
Sasaki does not disclose “wherein the first memory chip includes a first main input diode and a first main output diode electrically connected to the first main pad, and
an output terminal of the first main input diode is electrically connected to an input terminal of the first main output diode.”
Asano discloses: wherein the first memory chip (CP11) includes a first main input diode (D1a) and a first main output diode (D1b) electrically connected to the first main pad (PD1b), and an output terminal of the first main input diode (D1a) is electrically connected to an input terminal of the first main output diode (D1b), FIG. 5, [0035], [0040].
Asano [0035] discloses a junction between the resistor R1 and the internal circuit K1 is connected to diodes Da and Db with a common junction node. Therefore, the output of D1a is electrically connected to the input of D1b.
Asano discloses that a system as taught improves the electrostatic protection of the semiconductor chip [0035]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify Sasaki’s system in order to improve the electrostatic protection of the semiconductor chip as disclosed by Asano [0035].
Regarding Claim 11, The combination of Sasaki and Asano discloses the semiconductor system according to claim 1.
Sasaki does not explicitly disclose “wherein the first main pad is electrically connected to a controller configured to transmit a data signal to the first memory chip, by an external interconnection structure and a conductor ball.”
Asano discloses: wherein the first main pad (PD1b of memory chip CP1) is electrically connected to a controller (controller 1) configured to transmit a data signal to the first memory chip (CP1 including data terminals D1-D4, [0029]), by an external interconnection structure (Bus 2 and terminal T) and a conductor ball (bump electrode, [0023]), FIG. 1, [0022].
Asano discloses the controller 1 controls the NAND memories 3-1 to 3-n via a bus 2. The NAND memory 3-1 includes semiconductor chips CP1 to CPm, and each chip includes pad electrodes PD1 to PDm and data terminals D1-D4. Pads PD1 to PDm are connected to the terminal through bump electrodes, and the terminals are connected to the controller 1 via bus 2. This indicates that the first main pad PD1b is electrically connected to a controller 1 configured to transmit a data signal to a first memory chip CP1, by external interconnection (bus 2) and conductor ball (bump electrode), [0022], [0023], [0029].
Asano discloses that a system as taught prevents reduced operating frequency and increased power consumption [0041]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify Sasaki’s system in order to prevent reduced operating frequency and increased power consumption as disclosed by Asano [0041].
Regarding Claim 12, The combination of Sasaki and Asano discloses the semiconductor system according to claim 11.
Sasaki does not explicitly disclose “wherein the external interconnection structure is directly connected to each of the first main pad and the conductor ball, and electrically connects the first main pad and the conductor ball to each other.”
Asano discloses: wherein the external interconnection structure (Bus 2 and Terminal T) is directly connected to each of the first main pad (T is directly connected to PD1b) and the conductor ball (bump electrode), and electrically connects the first main pad (PD1b) and the conductor ball (bump electrode) to each other, FIGS. 1 & 5, [0022], [0023], [0040].
Asano discloses that a system as taught prevents reduced operating frequency and increased power consumption [0041]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify Sasaki’s system in order to prevent reduced operating frequency and increased power consumption as disclosed by Asano [0041].
Regarding Claim 13, The combination of Sasaki and Asano discloses the semiconductor system according to claim 1.
Sasaki does not disclose “wherein an electrostatic discharge characteristic of each of the first sub pad and the second sub pad is lower than an electrostatic discharge characteristic of each of the first main pad and the second main pad.”
Asano discloses first sub pad (PD1a) and the second sub pad (PD2b) and first main pad (PD1b) and the second main pad (PD2a), FIG. 5, [0040].
Asano [0041] discloses the electrostatic protection circuit CD1 of the semiconductor chip CP11 to be shared by the semiconductor chips CP11 to CP14. Accordingly, the electrostatic protection function of the semiconductor chips CP11 to CP14 can be secured by using only the electrostatic protection circuit CD1 of the semiconductor chip CP11. Further, the pad electrodes PD1b and PD2a to PD4a respectively connected to the internal circuits K11 to K14 can be commonly connected to the external terminal T21. This prevents that the capacitance of the electrostatic protection circuits CD2 to CD4 is added to the external terminal T21, without changing the structure of the semiconductor chips CP11 to CP14.
Therefore, the pads associated with the shared electrostatic protection circuit CD1 may have a higher electrostatic discharge
Asano discloses that a system as taught prevents the capacitance of additional electrostatic protection circuits from being added to the external terminal and reduces electrical power consumption [0041]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify Sasaki’s system in order to reduce electrical power consumption of the semiconductor system as disclosed by Asano [0041].
Regarding Claim 15, The combination of Sasaki and Asano discloses the semiconductor system according to claim 1.
Sasaki discloses: wherein a size of the second main pad (113b) is identical to a size of the first main pad (113a), and a size of the second sub pad (121b) is identical to a size of the first sub pad (121a), FIG. 1, [0054], [0060].
Sasaki [0054] discloses the plurality of electrode pads formed on the first memory chip 103a include a chip select pad 121a disposed on one end of the line of the plurality of electrode pads, and a plurality of control pads, address pads, or data pads 113a. Similarly, the plurality of electrode pads formed on the second memory chip 103b include a chip select pad 121b formed on one end of the line of the plurality of electrode pads, and four control pads, address pads, or data pads 113b.
Sasaki [0060] discloses the first memory chip 103a, the second memory chip 103b, and the third memory chip 103c each have the same planar shape and each include the same number of electrode pads arranged in the same manner. This indicates the size of the second main pad 113b may be identical to the size of the first main pad 113a, and the size of the second sub pad 121b may be identical to a size of the first sub pad 121a.
Regarding Claim 16, The combination of Sasaki and Asano discloses the semiconductor system according to claim 1.
Sasaki discloses: wherein each of the first memory chip (103a) and the one or more second memory chips (103b) includes at least one power pad (113a) connected to a separate power supply interconnection structure, [0027], [0058].
Sasaki [0027], [0058] discloses the pads 113a, 113b, 113c include a power supply and a ground. Sasaki [0058] discloses the pads 113a, 113b, 113c include a power supply terminal and a ground terminal. It would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to include a power pad in pads 113a which may be connected to separate power supply interconnection structure in order to connect to the power supply.
Regarding Claim 17, Sasaki discloses the semiconductor chip (semiconductor package 100, FIG. 1, [0051]) comprising:
Sasaki discloses a first memory chip (first memory chip 103a) including a first main pad (113a) and a first sub pad (121a) on first memory chip (103a), FIG. 1, [0054].
Asano [0029] discloses each of the semiconductor chips CP1 to CP4, includes pad electrodes PD1 to PD4 and data terminals D1-D4. It would be obvious to have the pad electrodes PD1b, PD2b, PD1a, and PD2a as data pads corresponding to data terminals D1-D4.
Asano discloses: a main data pad (PD1b) having a first electrostatic discharge characteristic, a sub data pad (PD1a) having a second electrostatic discharge characteristic lower than the first electrostatic discharge characteristic, FIG. 5, [0040].
Asano [0040] discloses the sub pads PD1a is connected to the internal circuits K11 via resistor R1a, and the main pads PD1b is connected to the internal circuits K11 to K14 via resistors R1b and electrostatic protection circuit CD1. Hence the first electrostatic discharge characteristic of the main pad may be higher than the second electrostatic discharge characteristic of the sub pad which is not connected to electrostatic protection circuit CD1.
and main data pad (PD1b) configured to receive a data signal from an external device (controller 1) outside the semiconductor chip (CP11), FIGS. 1 & 5, [0022], [0029];
Asano [0022] discloses a controller 1 that controls to drive the NAND memories 3-1 to 3-n via a bus 2 and the NAND memory 3-1 includes m semiconductor chips CP1 to CPm. Asano [0029] discloses the memory chips CP1 to CP4 includes data terminals D1 to D4, indicating the main data pad PD1b on the chip CP11 is configured to receive a data signal corresponding to the data terminals D1 to D4 from the external device (controller 1) outside the semiconductor chip (CP11).
and sub data pad (PD1a) electrically connected to the main data pad (PD1b). (through internal circuit K11), FIG. 5, [0040].
and configured to transmit the data signal to circuitry (K11) in semiconductor chip (CP11) through sub data pad (PD1a), FIG. 5, [0022], [0029], [0040].
Asano [0022] discloses a controller 1 that controls to drive the NAND memories 3-1 to 3-n via a bus 2 and the NAND memory 3-1 includes m semiconductor chips CP1 to CPm. Asano [0029] discloses the memory chips CP1 to CP4 includes data terminals D1 to D4. Asano [0040] discloses the sub pad PD1a is electrically connected to internal circuit K11. Thus, the sub pad PD1a on the chip CP11 is configured to transmit a data signal corresponding to data terminals D1 to D4 to the circuitry in the semiconductor chip CP11.
Asano discloses that a system as taught improves the electrostatic protection of the semiconductor chip [0047]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify Sasaki’s system in order to improve the electrostatic protection of the semiconductor chip as disclosed by Asano [0047].
Regarding Claim 18, The combination of Sasaki and Asano discloses the semiconductor chip according to claim 17.
Sasaki does not disclose “further comprising: a main input diode and a main output diode electrically connected to the main data pad, wherein an output terminal of the main input diode is electrically connected to an input terminal of the main output diode.”
Asano discloses: a main input diode (D1a) and a main output diode (D1b) electrically connected to the main data pad (PD1b), wherein an output terminal of the main input diode (D1a) is electrically connected to an input terminal of the main output diode (D1b), FIG. 5, [0035], [0040].
Asano [0035] discloses a junction between the resistor R1 and the internal circuit K1 is connected to diodes Da and Db with a common junction node. Therefore, the output of D1a is electrically connected to the input of D1b.
Asano discloses that a system as taught improves the electrostatic protection of the semiconductor chip [0035]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify Sasaki’s system in order to improve the electrostatic protection of the semiconductor chip as disclosed by Asano [0035].
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Sasaki in view of Asano further in view of Jeong et al. (US20210249382A1; hereinafter Jeong).
Regarding Claim 6, The combination of Sasaki and Asano discloses the semiconductor system according to claim 1.
The combination of Sasaki and Asano does not disclose “the one or more second memory chips are divided into a first group and a second group.”
In a similar art, Jeong discloses a semiconductor package comprising first and second stack structure including memory chips [0004].
Jeong discloses a semiconductor package 10 may include a package substrate 100, a semiconductor chip 200, first and second stack structures G1, G2 each including a plurality of memory chips, FIG. 2, [0018].
Jeong discloses: the one or more second memory chips are divided into a first group (300) and a second group (400), FIG. 2, [0028], [0033].
The combination of Sasaki, Asano, and Jeong discloses:
respective second sub pads of second memory chips (Asano: second sub pads PD2b, PD3b of chips CP12, CP13 respectively) included in the first group (Jeong: 300) are electrically connected to each other by a second internal interconnection structure (Asano: BW2, BW3, and T21, FIG. 5, [0040]).
and respective second sub pads of second memory chips (Asano: second sub pads PD2b, PD3b of chips CP12, CP13 respectively) included in the second group (Jeong: 400) are electrically connected to each other by a second internal interconnection structure (Asano: BW2, BW3, and T21, FIG. 5, [0040]).
and the second sub pad of one of the second memory chips (Asano: PD2b of CP12) included in the first group (Jeong: 300) and the second main pad of one second memory chip (Asano: PD2a of CP12) of the second memory chips included in the second group (Jeong: 400) are electrically connected to each other by a third internal interconnection structure (Jeong: wirings 110, 112, and chip 200, FIG. 2, [0020], [0042], [0043]).
Jeong [0020] discloses the package substrate 100 includes wirings 110, 112, 114, and 116 as channels for electrical connection between the semiconductor chip 200 and the memory chips. Jeong [0042] discloses the chips 300 of stack G1 may be electrically connected to semiconductor chip 200 by a first channel CH0 including wiring 110. Jeong [0043] discloses the chips 400 of the stack G2 may be electrically connected to the semiconductor chip 200 by a second channel CH1 including wiring 112. Therefore, the wirings 110 and 112, together with semiconductor chip 200 provide an electrical interconnection path between the memory chips in stacks G1 and G2.
Jeong discloses that a system as taught including groups of memory chip stacks decreases the entire thickness of the package [0048]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify Sasaki and Asano’s system in order to reduce the entire thickness of the package as disclosed by Jeong [0048].
Claims 8-10 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Sasaki in view of Asano further in view of Seta (US20140071567A1; hereinafter Seta).
Regarding Claim 8, The combination of Sasaki and Asano discloses the semiconductor system according to claim 7.
Asano discloses first memory chip (CP11) includes a first main pad PD1b, a first sub pad PD1a, a first main input diode (D1a) and a first main output diode (D1b), FIG. 5, [0040].
The combination of Sasaki and Asano does not disclose “wherein the first memory chip includes a first sub input diode and a first sub output diode electrically connected to the first sub pad, and an input terminal of the first sub input diode is electrically connected to the input terminal of the first main output diode.”
In a similar art, Seta discloses a semiconductor device with plurality of pads and ESD protection circuits [0016].
Seta discloses the pads 2c1 and 2c2 are connected to the one electrode 102 and are used for inputting one input signal, and each pad is connected to ESD protection circuits 12 including diodes Dp and Dn through wirings L1 and L2. The pad 2c2 is connected to diodes Dp and Dn through wiring L2, FIG. 3, [0025], [0030], [0039]. Dp is interpreted as the first sub input diode, and Dn is interpreted as the first sub output diode.
The combination of Sasaki, Asano and Seta discloses: wherein the first memory chip (Asano: CP11) includes a first sub input diode (Seta: Dp) and a first sub output diode (Seta: Dn) electrically connected to the first sub pad (connection point P2 of diodes Dp and Dn connected to Asano’s first sub pad PD1a).
and an input terminal of the first sub input diode (Seta: input terminal P2 of diode Dp) is electrically connected to the input terminal of the first main output diode (common junction of D1a and D1b of circuit CD1 on Asano’s chip CP11, FIG. 5, [0040]).
Seta discloses that a system as taught improves the ESD protection of the semiconductor chip [0039]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify Sasaki and Asano’s system in order to improve the ESD protection of the semiconductor chip as disclosed by Seta [0039].
Regarding Claim 9, The combination of Sasaki, Asano, and Seta discloses the semiconductor system according to claim 8.
The combination of Sasaki and Asano does not disclose “wherein an output terminal of the first sub input diode is not electrically connected to an input terminal of the first sub output diode.”
Seta discloses: wherein an output terminal of the first sub input diode (output terminal of Dp is connected to Vdd) is not electrically connected to an input terminal of the first sub output diode (input terminal of Dn is connected to Vss), FIG. 3, [0031].
Seta discloses that a system as taught improves the ESD protection of the semiconductor chip [0039]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify Sasaki and Asano’s system in order to improve the ESD protection of the semiconductor chip as disclosed by Seta [0039].
Regarding Claim 10, The combination of Sasaki, Asano and Seta discloses the semiconductor system according to claim 8.
Asano discloses: wherein each of the one or more second memory chips (CP12) includes: a second main input diode (D2a) and a second main output diode (D2b) of circuit CD2 electrically connected to the second main pad (PD2a), FIG. 5, [0040].
The combination of Sasaki and Asano does not disclose “a second sub input diode and a second sub output diode electrically connected to the second sub pad, and wherein an input terminal of the second sub input diode is electrically connected to an input terminal of the second main output diode.”
Seta discloses the pads 2c1 and 2c2 are connected to the one electrode 102 and are used for inputting one input signal, and each pad is connected to ESD protection circuits 12 including diodes Dp and Dn through wirings L1 and L2. The pad 2c2 is connected to diodes Dp and Dn through wiring L2, FIG. 3, [0025], [0030], [0039]. Dp is interpreted as the second sub input diode, and Dn is interpreted as the second sub output diode.
The combination of Sasaki, Asano and Seta discloses:
a second sub input diode (Seta: Dp) and a second sub output diode (Seta: Dn) electrically connected to the second sub pad (Asano: PD2b on chip CP12).
wherein an input terminal of the second sub input diode (Seta: input terminal P2 of diode Dp) is electrically connected to an input terminal of the second main output diode (common junction of D2a and D2b of circuit CD2 on Asano’s chip CP12, FIG. 5, [0040]).
Seta discloses that a system as taught improves the ESD protection of the semiconductor chip [0039]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify Sasaki and Asano’s system in order to improve the ESD protection of the semiconductor chip as disclosed by Seta [0039].
Regarding Claim 19, The combination of Sasaki and Asano semiconductor chip according to claim 18.
The combination of Sasaki and Asano does not disclose “further comprising:
a sub input diode and a sub output diode electrically connected to the sub data pad, wherein an input terminal of the sub input diode is electrically connected to the input terminal of the main output diode.”
Asano discloses first memory chip (CP11) includes a first main pad PD1b, a first sub pad PD1a, a first main input diode (D1a) and a first main output diode (D1b), FIG. 5, [0040].
Seta discloses the pads 2c1 and 2c2 are connected to the one electrode 102 and are used for inputting one input signal, and each pad is connected to ESD protection circuits 12 including diodes Dp and Dn through wirings L1 and L2. The pad 2c2 is connected to diodes Dp and Dn through wiring L2, FIG. 3, [0025], [0030], [0039]. Dp is interpreted as the sub input diode, and Dn is interpreted as the sub output diode.
The combination of Sasaki, Asano and Seta discloses: a sub input diode (Dp) and a sub output diode (Dn) electrically connected to the sub pad (Asano: PD1a),
wherein an input terminal of the sub input diode (Seta: connection point P2 is the input terminal of Dp) is electrically connected to the input terminal of the main output diode (common junction of D1a and D1b of circuit CD1 on Asano’s chip CP11, FIG. 5, [0040]).
Seta discloses that a system as taught improves the ESD protection of the semiconductor chip [0039]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify Sasaki and Asano’s system in order to improve the ESD protection of the semiconductor chip as disclosed by Seta [0039].
Claims 14 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Sasaki in view of Asano further in view of Kim (US5925935A; hereinafter Kim).
Regarding Claim 14, The combination of Sasaki and Asano discloses the semiconductor system according to claim 1.
Asano discloses first sub pad (PD1a) and the second sub pad (PD2b) and first main pad (PD1b) and the second main pad (PD2a), FIG. 5, [0040].
The combination of Sasaki and Asano does not disclose “wherein a size of the first sub pad is smaller than a size of the first main pad, and a size of the second sub pad is smaller than a size of the second main pad.”
In a similar art, Kim discloses a semiconductor chip 130 [Col. 5, line 62].
The combination of Sasaki, Asano, and Kim discloses: wherein a size of the first sub pad (Asano: PD1a) is smaller than a size of the first main pad (Asano: PD1b), and a size of the second sub pad (Asano: PD2b) is smaller than a size of the second main pad (Asano: PD2a), (Kim: [Col. 5, line 62], FIG. 16).
Kim ([Col. 5, line 62], FIG. 16) discloses the semiconductor chip 130 has a structure in which the width distance 134' of each end bonding pad 134 is twice the width distance of the interior bonding pad 132. For example, the area of each end bonding pad 134 is 128 μm X 80 μm, and the area of each interior bonding pad 132 is 64 μm X 80 μm. This indicates the sub pads may be smaller than the main pads in the Sasaki and Asano’s semiconductor system.
Kim discloses that a system as taught reduces the semiconductor chip size and the manufacturing cost [Col. 1, line 21]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify Sasaki and Asano’s system in order to reduce the semiconductor chip size and the manufacturing cost as disclosed by Kim [Col. 1, line 21].
Regarding Claim 20, The combination of Sasaki and Asano discloses the semiconductor chip according to claim 17.
The combination of Sasaki and Asano does not disclose “wherein a size of the sub data pad is smaller than a size of the main data pad.”
Asano [0029] discloses each of the semiconductor chips CP1 to CP4, includes pad electrodes PD1 to PD4 and data terminals D1-D4. It would be obvious to have the pad electrodes PD1b, PD2b, PD1a, and PD2a as data pads corresponding to data terminals D1-D4.
The combination of Sasaki, Asano, and Kim discloses: wherein a size of a sub pad (Asano: PD1a) is smaller than a size of the main pad (Asano: PD1b).
Kim ([Col. 5, line 62], FIG. 16) discloses the semiconductor chip 130 has a structure in which the width distance 134' of each end bonding pad 134 is twice the width distance of the interior bonding pad 132. For example, the area of each end bonding pad 134 is 128 μm X 80 μm, and the area of each interior bonding pad 132 is 64 μm X 80 μm. This indicates the sub pads may be smaller than the main pads in the Sasaki and Asano’s system.
Kim discloses that a system as taught reduces the semiconductor chip size and the manufacturing cost [Col. 1, line 21]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify Sasaki and Asano’s system in order to reduce the semiconductor chip size and the manufacturing cost as disclosed by Kim [Col. 1, line 21].
Conclusion
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/Krishna J. Palaniswamy/
Examiner, Art Unit 2899
/Brent A. Fairbanks/Supervisory Patent Examiner, Art Unit 2899
Prosecution Insights