Prosecution Insights
Last updated: April 19, 2026
Application No. 18/483,525

MEMORY DEVICE INCLUDING A PAGE BUFFER

Non-Final OA §102§103§112
Filed
Oct 10, 2023
Examiner
HUANG, MIN
Art Unit
2827
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
SK Hynix Inc.
OA Round
3 (Non-Final)
90%
Grant Probability
Favorable
3-4
OA Rounds
2y 2m
To Grant
99%
With Interview

Examiner Intelligence

Grants 90% — above average
90%
Career Allow Rate
743 granted / 824 resolved
+22.2% vs TC avg
Moderate +10% lift
Without
With
+9.9%
Interview Lift
resolved cases with interview
Typical timeline
2y 2m
Avg Prosecution
18 currently pending
Career history
842
Total Applications
across all art units

Statute-Specific Performance

§101
2.7%
-37.3% vs TC avg
§103
54.3%
+14.3% vs TC avg
§102
24.2%
-15.8% vs TC avg
§112
8.4%
-31.6% vs TC avg
Black line = Tech Center average estimate • Based on career data from 824 resolved cases

Office Action

§102 §103 §112
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Allowable Subject Matter Claim 2-7 and 11-15 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Response to Arguments Applicant’s arguments with respect to claim(s) have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claim 16 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claim 16 recites the limitation " the first node". There is insufficient antecedent basis for this limitation in the claim. Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 1, 8 and 17 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Cha (PGPUB 20130163332), hereinafter as Cha. Regarding claim 1, Cha teaches a memory device, comprising: a cell string comprising a plurality of memory cells (Fig 4, BLe/Blo); and a page buffer (Fig 5, PB) coupled to the cell string, the page buffer comprising a latch with cross-coupled transistors (Fig 5, L1/L2 with cross coupled transistors), wherein data corresponding to a read voltage and transferred from the cell string to the page buffer is input to gates of plural transistors (Fig 4, SO connected to BLe/BLo, and to gates N21/N17/N20 which are not part of cross coupled latches L1/L2), other than the cross-coupled transistors, included in the page buffer. Regarding claim 8/17, Cha teaches each of the memory cells is configured to store multi-bit data ([0260]), and wherein the data transferred from the cell string includes 1-bit data which is recognized by the a-read voltage among the multi-bit data when the read voltage is applied to at least one of the memory cells (Fig 7). Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 9, 19-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Cha. Regarding claim 9, Cha teaches a memory device, comprising: a cell string comprising plural memory cells (Fig 4); a page buffer (Fig 5, PB) coupled to the cell string, the page buffer comprising a latch with cross-coupled transistors (Fig5, L1/L29 ); voltage generation circuitry (Fig 3, voltage supply circuit 305) configured to generate a read voltage and a pass voltage (it is well known in the field, word lines are applied with different voltages for a read operation of a NAND string); and control circuitry (Fig 3, controller 306) configured to generate a control signal to be input to the page buffer and the voltage generation circuitry (Fig 3), wherein data corresponding to the read voltage and transferred from the cell string to the page buffer is input to gates of plural transistors, other than the cross-coupled transistors (Fig 5, N21/N17/N20 gate not part of L1/L2), and input page buffer (Fig 5, N43), Regarding claim 19, Cha teaches the cell string and the page buffer is coupled to each other through a bit line and a sensing output node (Fig 5, SO), and wherein the memory device further comprises: precharge circuitry configured to precharge the bit line and the sensing output node (Fig 5, P1 and N6); and at least one switch (Fig 5, N5) configured to control connection between the bit line and the sensing output node. Regarding claim 20, Oh teaches the at least one switch is controlled by a signal output from the control circuitry (Fig 5, PB_SENSE is generated by the controller in Fig 3). Claim(s) 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Cha, in view of Tanzawa (PGPUB 20170229180), hereinafter as Tanzawa. Regarding claim 18, Cha teaches a memory device as in rejection of claim 9, But not expressly the page buffer and at least one another page buffer are coupled to the cell string, and a number of page buffers coupled to the cell string is equal to or greater than a number of bits of data stored in each memory cell. Tanzawa teaches the page buffer and at least one another page buffer are coupled to the cell string, and a number of page buffers coupled to the cell string is equal to or greater than a number of bits of data stored in each memory cell (Fig 1, at least [0037)). Since Tanzawa and Cha are both from the same field of IC memory device, the purpose disclosed by Tanzawa would have been recognized in the pertinent art of Cha. It would have been obvious at the time the invention was filed to a person having ordinary skill in the art to use multiple PB for a bit line as in Tanzawa into the device of Cha for the purpose of reading multi bit data stored in a memory cell. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to MIN HUANG whose telephone number is (571)270-5798. The examiner can normally be reached M-F 9-6. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Amir Zarabian can be reached at (571)272-1852. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /MIN HUANG/Primary Examiner, Art Unit 2827
Read full office action

Prosecution Timeline

Oct 10, 2023
Application Filed
Jun 10, 2025
Non-Final Rejection — §102, §103, §112
Sep 12, 2025
Response Filed
Sep 21, 2025
Final Rejection — §102, §103, §112
Dec 13, 2025
Interview Requested
Dec 16, 2025
Applicant Interview (Telephonic)
Dec 16, 2025
Examiner Interview Summary
Dec 23, 2025
Request for Continued Examination
Jan 15, 2026
Response after Non-Final Action
Jan 19, 2026
Non-Final Rejection — §102, §103, §112 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12603114
MEMORY DEVICE
2y 5m to grant Granted Apr 14, 2026
Patent 12597464
SRAM WITH PUF DEDICATED SECTOR STANDING-BY
2y 5m to grant Granted Apr 07, 2026
Patent 12597465
MEMORY DEVICE
2y 5m to grant Granted Apr 07, 2026
Patent 12592273
Usage-Based Disturbance Mitigation
2y 5m to grant Granted Mar 31, 2026
Patent 12586652
ESTIMATING PEAK SOURCE CURRENT USING MEMORY DIE SUBSTRATE TEMPERATURE DETECTION
2y 5m to grant Granted Mar 24, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

AI Strategy Recommendation

Get an AI-powered prosecution strategy using examiner precedents, rejection analysis, and claim mapping.
Powered by AI — typically takes 5-10 seconds

Prosecution Projections

3-4
Expected OA Rounds
90%
Grant Probability
99%
With Interview (+9.9%)
2y 2m
Median Time to Grant
High
PTA Risk
Based on 824 resolved cases by this examiner. Grant probability derived from career allow rate.

Sign in with your work email

Enter your email to receive a magic link. No password needed.

Personal email addresses (Gmail, Yahoo, etc.) are not accepted.

Free tier: 3 strategy analyses per month