DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Allowable Subject Matter
Claim 2-7 and 11-15 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Response to Arguments
Applicant’s arguments with respect to claim(s) have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 16 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 16 recites the limitation " the first node". There is insufficient antecedent basis for this limitation in the claim.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 8 and 17 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Cha (PGPUB 20130163332), hereinafter as Cha.
Regarding claim 1, Cha teaches a memory device, comprising:
a cell string comprising a plurality of memory cells (Fig 4, BLe/Blo); and
a page buffer (Fig 5, PB) coupled to the cell string, the page buffer comprising a latch with cross-coupled transistors (Fig 5, L1/L2 with cross coupled transistors), wherein data corresponding to a read voltage and transferred from the cell string to the page buffer is input to gates of plural transistors (Fig 4, SO connected to BLe/BLo, and to gates N21/N17/N20 which are not part of cross coupled latches L1/L2), other than the cross-coupled transistors, included in the page buffer.
Regarding claim 8/17, Cha teaches each of the memory cells is configured to store multi-bit data ([0260]), and wherein the data transferred from the cell string includes 1-bit data which is recognized by the a-read voltage among the multi-bit data when the read voltage is applied to at least one of the memory cells (Fig 7).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 9, 19-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Cha.
Regarding claim 9, Cha teaches a memory device, comprising:
a cell string comprising plural memory cells (Fig 4);
a page buffer (Fig 5, PB) coupled to the cell string, the page buffer comprising a latch with cross-coupled transistors (Fig5, L1/L29 );
voltage generation circuitry (Fig 3, voltage supply circuit 305) configured to generate a read voltage and a pass voltage (it is well known in the field, word lines are applied with different voltages for a read operation of a NAND string); and
control circuitry (Fig 3, controller 306) configured to generate a control signal to be input to the page buffer and the voltage generation circuitry (Fig 3),
wherein data corresponding to the read voltage and transferred from the cell string to the page buffer is input to gates of plural transistors, other than the cross-coupled transistors (Fig 5, N21/N17/N20 gate not part of L1/L2), and input page buffer (Fig 5, N43),
Regarding claim 19, Cha teaches the cell string and the page buffer is coupled to each other through a bit line and a sensing output node (Fig 5, SO), and wherein the memory device further comprises: precharge circuitry configured to precharge the bit line and the sensing output node (Fig 5, P1 and N6); and at least one switch (Fig 5, N5) configured to control connection between the bit line and the sensing output node.
Regarding claim 20, Oh teaches the at least one switch is controlled by a signal output from the control circuitry (Fig 5, PB_SENSE is generated by the controller in Fig 3).
Claim(s) 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Cha, in view of Tanzawa (PGPUB 20170229180), hereinafter as Tanzawa.
Regarding claim 18, Cha teaches a memory device as in rejection of claim 9,
But not expressly the page buffer and at least one another page buffer are coupled to the cell string, and a number of page buffers coupled to the cell string is equal to or greater than a number of bits of data stored in each memory cell.
Tanzawa teaches the page buffer and at least one another page buffer are coupled to the cell string, and a number of page buffers coupled to the cell string is equal to or greater than a number of bits of data stored in each memory cell (Fig 1, at least [0037)).
Since Tanzawa and Cha are both from the same field of IC memory device, the purpose disclosed by Tanzawa would have been recognized in the pertinent art of Cha.
It would have been obvious at the time the invention was filed to a person having ordinary skill in the art to use multiple PB for a bit line as in Tanzawa into the device of Cha for the purpose of reading multi bit data stored in a memory cell.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MIN HUANG whose telephone number is (571)270-5798. The examiner can normally be reached M-F 9-6.
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/MIN HUANG/Primary Examiner, Art Unit 2827