Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 9 and 16 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
As to claims 9 and 16, recitation of wherein a grain size of crystal particles of the plate portion is greater than or equal to a grain size of the crystal particles of the via portion is unclear since it is unclear if applicant is requiring the material to be polycrystalline. Amorphous semiconductors and single crystal semiconductors do not have a grain size since there are no grains. Crystal particles lack antecedent basis in both the plate and via portion. The examiner will interpret the claim to mean the via and plate comprise polycrystalline material and a grain size of crystal particles of the plate portion is greater than or equal to a grain size of the crystal particles of the via portion
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-6 and 10-11 is/are rejected under 35 U.S.C. 102 a1 as being anticipated by Oh 20220359564.
Oh teaches A semiconductor device, comprising: a semiconductor substrate (figure 4b item 201); a peripheral circuit structure on the semiconductor substrate (item 200); and a cell array structure on the peripheral circuit structure (item MCA), the cell array structure comprising: a stack comprising interlayer insulating layers (items 109 figure 3A) and conductive patterns (item 107) that are vertically and alternately stacked (see figure 4b and 3A); a first upper insulating layer on the stack (a portion of item 105a ); vertical channel patterns that extend through the stack and the first upper insulating layer (item 125); and a source structure on the first upper insulating layer and connected to the vertical channel patterns (item 185), wherein the source structure comprises a first semiconductor layer (items 185 see figures include figure 3B, and figures 5)), wherein the first semiconductor layer comprises a plate portion on the first upper insulating layer (items 185hp), and wherein the first semiconductor layer comprises a via portion that extends through the first upper insulating layer and is connected to the vertical channel patterns (item 185cp).
b. AS to claim 2, Oh teaches wherein the cell array structure further comprises a data storage pattern on the vertical channel patterns (item 121H), and a distance of an upper surface of the data storage pattern from the semiconductor substrate is greater than a distance of an upper surface of the vertical channel patterns from the semiconductor substrate (figure 3B shows 121A extending above the top of item 125A).
c. AS to claim 3, Applicant has not set forth the second different the first. Oh, therefore teaches wherein the source structure further comprises a second semiconductor layer below the first semiconductor layer (a portion of 185CP in contact with 125A or a portion of item 125A in contact with 185CP), and the via portion is connected to the vertical channel pattern by the second semiconductor layer (by definition).
d. As to claim 4, Oh teaches wherein a width of the via portion is less than a width of the upper surface of the vertical channel pattern (specifically due to the nature of the taper the portion of 185CP in contact with 185HP will be less than that of 125A that contacts 185CP thus there is a width of 185CP that is less than the width of upper surface of the vertical channel).
e. As to claim 5, Oh teaches wherein a portion of the vertical channel pattern comprises a first outer side surface(edge on which A1 is on), and the data storage pattern is on the first outer side surface of the vertical channel pattern (121A is on the outer edge).
f. As to claim 6, Oh teaches wherein a portion of the data storage pattern comprises a second outer side surface, and the first upper insulating layer is on the second outer side surface of the data storage pattern (see e.g. figure 3B the outer portion of item 121 is in contact with 105).
g. As to claim 10, Oh teaches wherein the peripheral circuit structure comprises peripheral circuits on the semiconductor substrate and first bonding pads connected to the peripheral circuits (item 231 figure 4b), and the cell array structure further comprises second bonding pads connected to the first bonding pads (item 155 figure 4b).
h. As to claim 11, Oh teaches wherein the source structure further comprises a metal layer covering the first semiconductor layer (figure 4A item 191).
Claim(s) 1,2,5,6 and 7 is/are rejected under 35 U.S.C. 102a1 as being anticipated by Arai (20220406811).
a. As to claim 1, Arai teaches A semiconductor device, comprising: a semiconductor substrate (figure 4 item 50); a peripheral circuit structure on the semiconductor substrate (Tr figure 4); and a cell array structure on the peripheral circuit structure (MR figure 4), the cell array structure comprising: a stack comprising interlayer insulating layers and conductive patterns that are vertically and alternately stacked (items 21 and 31 alternating); a first upper insulating layer on the stack (top item 21 or 70 in figure 6B); vertical channel patterns that extend through the stack and the first upper insulating layer (item 41); and a source structure on the first upper insulating layer and connected to the vertical channel patterns (item 30), wherein the source structure comprises a first semiconductor layer (item 30 paragraph 56 P-doped silicon (Si)), wherein the first semiconductor layer comprises a plate portion on the first upper insulating layer (item 30 flat portion figure 6B) , and wherein the first semiconductor layer comprises a via portion that extends through the first upper insulating layer and is connected to the vertical channel patterns (item 30a).
b. As to claim 2, Arai teaches wherein the cell array structure further comprises a data storage pattern on the vertical channel patterns (item 42 figure 6B), and a distance of an upper surface of the data storage pattern from the semiconductor substrate is greater than a distance of an upper surface of the vertical channel patterns from the semiconductor substrate (42 extends higher that 41).
c. As to claim 5, Arai teaches wherein a portion of the vertical channel pattern comprises a first outer side surface, and the data storage pattern is on the first outer side surface of the vertical channel pattern (item 42 is on an outer surface of item 41 figure 6B).
d. As to claim 6, Arai teaches wherein a portion of the data storage pattern comprises a second outer side surface, and the first upper insulating layer is on the second outer side surface of the data storage pattern (figure 6B item 71 is on the outer edge of 42).
e. As to claim 7 , Arai teaches wherein the first upper insulating layer is on the upper surface of the data storage pattern( at the step region of 42 item 71 is on the upper portion of the step).
Claim(s) 1, 11-15, and 18 is/are rejected under 35 U.S.C. 102a1 as being anticipated by Ryu (20220344244).
a. As to claim 1, Ryu teaches A semiconductor device, comprising: a semiconductor substrate (figure 2A item 10); a peripheral circuit structure on the semiconductor substrate (item 50); and a cell array structure on the peripheral circuit structure (item 2 stack on item 1), the cell array structure comprising: a stack comprising interlayer insulating layers (items 120M) and conductive patterns (items 130) that are vertically and alternately stacked (figure 2A); a first upper insulating layer on the stack (item 120U); vertical channel patterns that extend through the stack and the first upper insulating layer (CH); and a source structure on the first upper insulating layer and connected to the vertical channel patterns (item 200 see also figure 5A), wherein the source structure comprises a first semiconductor layer (paragraph 30), wherein the first semiconductor layer comprises a plate portion on the first upper insulating layer (items 200 and 200L), and wherein the first semiconductor layer comprises a via portion that extends through the first upper insulating layer and is connected to the vertical channel patterns (item 200p1 relative to 120U).
b. As to claim 11, Ryu teaches wherein the source structure further comprises a metal layer covering the first semiconductor layer (item 205 paragraph 54).
c. As to claim 12 Ryu further teaches wherein the cell array structure comprises: a second upper insulating layer on the source structure (item 210 figure 2A); an input/output contact plug laterally spaced apart from the stack and the source structure and connected to the peripheral circuit structure (items 160p and 160s); and an input/output pad on the second upper insulating layer and connected to the input/output contact plug (items 230 and 220).
d. As to claim 13, Ryu teaches A semiconductor device, comprising: a semiconductor substrate (figure 2A item 10); a peripheral circuit structure on the semiconductor substrate (item 1 or 50); and a cell array structure on the peripheral circuit structure (item 2), the cell array structure comprising: a stack comprising interlayer insulating layers and conductive patterns that are vertically and alternately stacked (items 120M and 130M); an upper insulating layer on the stack (item 120U and upper portions of item 191)); vertical structures that extend through the stack and the upper insulating layer (item CH), each of the vertical structures comprising a vertical channel pattern (item CH/147/140 figure 5A) and a data storage pattern on the vertical channel pattern (item 145 in particular item 142); a source structure on the upper insulating layer and connected to the vertical channel patterns of the vertical structures (item 200); and a peripheral contact plug laterally spaced apart from the stack and the source structure and connected to the peripheral circuit structure (item 160), wherein the peripheral contact plug comprises a first protruding portion that extends through the upper insulating layer (items 160S), and wherein the upper insulating layer is on the data storage pattern (item 120U figure 5A) and a side surface of the first protruding portion (item 191).
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e. As to claim 14, Ryu teaches wherein the data storage pattern is between the upper insulating layer and the vertical channel pattern (figure 5A item 145 is between 120U and item 140).
f. As to claim 15 Ryu teaches wherein the source structure comprises a first semiconductor layer and a second semiconductor layer on the first semiconductor layer (this is arbitrary since applicant does not any difference between the first and the second thus 200 away from 205 can be the second and the first can be 200 near or adjacent 205)),the second semiconductor layer comprises a plate portion on the upper insulating layer and a via portion that extends through the upper insulating layer (item 200 in figure 5A), and the via portion of the second semiconductor layer is connected to the vertical channel patterns by the first semiconductor layer (200p1).
g. As to claim 18 Ryu teaches wherein the peripheral circuit structure comprises peripheral circuits on the semiconductor substrate and first bonding pads connected to the peripheral circuits (item 40), and the cell array structure further comprises second bonding pads connected to the first bonding pads (item 180).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ryu in view of in view of Xiao (20220068882)
Ryu does not explicitly teach wherein the cell array structure comprises an input/output contact plug that is laterally spaced apart from the stack, the source structure, and the peripheral contact plug, the input/output contact plug is connected to the peripheral circuit structure, the input/output contact plug comprises a second protruding portion that extends through the upper insulating layer, and the upper insulating layer is on a side surface of the second protruding portion.
Xiao teaches having a plurality of pads (items 123 and 122) and plugs (items 170) spaced apparat from the stack and each other (figure 1 including the source and the other plug item 122 ,123 and 105 and space apart from one another)
Thus it would have been obvious to one of ordinary skill in the art at the time of filing to provide wherein the cell array structure comprises an input/output contact plug that is laterally spaced apart from the stack (an additional pad), the source structure, and the peripheral contact plug (as suggest by Xiao figure 1), the input/output contact plug is connected to the peripheral circuit structure (as suggested by Xiao figure 1), the input/output contact plug comprises a second protruding portion that extends through the upper insulating layer, and the upper insulating layer is on a side surface of the second protruding portion (as item 160 and 191 of Ryu).
One would have been so motivated to allow for additional access to memory allowing multiple functions to be implemented simultaneously between a host and the memory.
Claim(s) 19-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ryu in view of Arai.
g. As to claim 19 Ryu teaches An electronic system, comprising: a semiconductor device comprising a semiconductor substrate (figure 2A item 10), a peripheral circuit structure on the semiconductor substrate (item 50 or item 1 as a whole), and a cell array structure on the peripheral circuit structure (item 2); and a controller that is electrically connected to the semiconductor device by an input/output pad (figure 17 item 1200 via 1101), wherein the peripheral circuit structure comprises peripheral circuits that are on the semiconductor substrate (item 50 or item 1), and wherein the peripheral circuit structure comprises first bonding pads that are connected to the peripheral circuits (items 40), wherein the cell array structure comprises: second bonding pads connected to the first bonding pads (items 180); a stack on the second bonding pads, the stack comprising interlayer insulating layers and conductive patterns that are vertically and alternately stacked on the second bonding pads (items 120M and 130M); an upper insulating layer on the stack (item 120U); vertical structures that extend through the stack and the upper insulating layer (CH); and a source structure on the upper insulating layer and connected to the vertical structures (items 200), wherein the source structure comprises a first semiconductor layer and a second semiconductor layer on the first semiconductor layer (this is arbitrary portion of 200 can be considered the first and other portion the second), wherein the second semiconductor layer comprises a plate portion (figure 5A item 200 and 200L) and a via portion that extends through the upper insulating layer and is connected to the vertical structure (item 200p1 figure 5A), wherein each of the vertical structures comprises a vertical channel pattern and a data storage pattern on the vertical channel pattern (items 145 on the channel item 140),
Ryu does not teach wherein a distance of an upper surface of the data storage pattern from the semiconductor substrate is greater than a distance of an upper surface of the vertical channel pattern from the semiconductor substrate.
Arai teaches wherein a distance of an upper surface of the data storage (item 142 figure 6B) pattern from the semiconductor substrate is greater than a distance of an upper surface of the vertical channel pattern from the semiconductor substrate (item 41) and wherein the data storage pattern is on at least a portion of an upper surface of the vertical channel pattern (item 70 on 42 figure 6B).
Further Arai teaches paragraph 115:
In the semiconductor storage device 1 according to the first embodiment, the interface between the second conductive layer 30 and the upper surface 41a of the semiconductor channel 41 is located lower than the upper surface of the stack 20. Thus, it is possible to appropriately apply a voltage to a barrier portion for electrons flowing into the semiconductor channel 41 (the interface between a metal and a semiconductor), which may prevent deterioration of cell current.
Thus it would have been obvious to one of ordinary skill in the art to implement as suggested by Arai wherein a distance of an upper surface of the data storage (item 142 figure 6B) pattern from the semiconductor substrate is greater than a distance of an upper surface of the vertical channel pattern from the semiconductor substrate (item 41) and wherein the data storage pattern is on at least a portion of an upper surface of the vertical channel pattern (item 70 on 42 figure 6B) to prevent deterioration of the cell current as suggest by Arai.
Allowable Subject Matter
Claim 8 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
As to claim 8, Prior art fails to teach and or suggest wherein the source structure further comprises a second semiconductor layer below the first semiconductor layer, the via portion and the second semiconductor layer comprise a polycrystalline semiconductor material, and a grain size of crystal particles of the second semiconductor layer is greater than or equal to a grain size of crystal particles of the via portion.
Claims 9 and 16 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
Prior art fails to teach that the plate portion and via portion comprise polycrystalline semiconductor material and a grain size of crystal particles of the plate portion is greater than or equal to a grain size of the crystal particles of the via portion.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Cheng et al. 20200350321 teaches extending the upper insulator top of 704 into the contact area 810.
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/MATTHEW L. REAMES/
Primary Examiner
Art Unit 2896
/MATTHEW L REAMES/Primary Examiner, Art Unit 2896